HARSHIT KUMAR SINGH

Product Engineer

Hyderabad, Telangana, India3 yrs 9 mos experience

Key Highlights

  • Expert in VLSI design verification and power optimization.
  • Proficient in SystemVerilog and hardware verification.
  • Strong background in semiconductor technology and automation.
Stackforce AI infers this person is a Semiconductor Engineer with expertise in VLSI design and hardware verification.

Contact

Skills

Core Skills

Hardware VerificationPower OptimizationSystemverilogDdr Sdram

Other Skills

Power ExecutionAutomation CodingPC Computer ArchitectureHardware Board Bring UpSilicon Power CharacterizationLab EnvironmentTest ProceduresOrganization SkillsInterconnectIP Multimedia SubsystemiOSSystem TestingSerDesSignal ProcessingTransistors

About

Looking for a role in vlsi design verification Engineer

Experience

3 yrs 9 mos
Total Experience
2 yrs
Average Tenure
1 yr 9 mos
Current Experience

Qualcomm

PPAT Engineer(Post Si Validation)

Sep 2024Present · 1 yr 9 mos · Хайдарабад · On-site

  • Working in Qualcomm QCT SOC PPA Team
Hardware Verification

Qualcomm india private limited

Analysis Specialist

Sep 2024Present · 1 yr 9 mos

  • Working in Power Performance and Analysis team, doing Power Execution of Modem in LTE Dashboard and working across power optimization of DYNAMIC and LEAKAGE power use cases with different scenarios and 5G NR scenarios and proposed few optimization techniques to save Chipset Power in different scenarios especially in Data use cases and also developing automation coding for different scenarios
  • Experience of working and collaborating with HW and SW teams to do the vital tuning and optimization of silicon power, for an example implementing the concept of TCP Keep alive offload feature meaning client and Server communication between two hardware keeping system level suspend ande offloading packets to modem.
  • Knowledge of PC Computer architecture and various commonly used buses like APB, AXI, Serdes and PCIE.
  • Experience of Hardware Board bring up working in two projects with direct impact to customers, also knowledge of power on sequence flow, dip switches, CDT fuse and concepts related to bring up.
  • Being from VLSI Background, strong understanding of aspects related to silicon power and performance, characterization of parts like typical-typical, slow-slow and fast-fast msms, technology node impacts like working on cadence software for 90nm, 65nm design, also have knowledge of 5nm, 3nm, 2nm and 1nm technology node design, also have knowledge of quantum nodes used in GaAs(Gate ALL AQROUND SEMICONDUCTORS).
  • Experience working in Lab Environment and ready to come 5 days in office and understanding of various lab equipment like JTAG,power supply adapter, callboxes and oscilloscopes.
Power ExecutionPower OptimizationAutomation CodingPC Computer ArchitectureHardware Board Bring UpSilicon Power Characterization+2

Samsung semiconductor research and development

Student Trainee

Jan 2024Jul 2024 · 6 mos · Bengaluru, Karnataka, India · On-site

  • Has developed uvm scoreboard for cadence DFI part in LPDDR5 protocol ,Developing perl and TCL based automation scripts.
SystemVerilogDDR SDRAMTest ProceduresOrganization SkillsInterconnectIP Multimedia Subsystem+22

Samsung semiconductor india research

Design Verification Engineer

Jan 2024Jul 2024 · 6 mos

  • • During my internship, I gained valuable insight into implement and analyze System Verilog assertion and coverage (code, toggle, functional). Additionally, I developed a proficient understanding of inter-core communication facilitated by standard AMBA protocols (especially APB protocol and AHB protocol ,AXI Protocol).

Cognizant technology solutions

Programmer Analyst

Aug 2020Aug 2022 · 2 yrs · Kolkata, West Bengal, India · On-site

  • Working as a Programmer Analyst in Cognizant

Cognizant

Programming Analyst

Aug 2020Aug 2022 · 2 yrs

  • Has worked as a Programmer Analyst, handling client-based role in Cognizant with role of Quality Analyst developing Selenium Scripts, transitioning UFT Scripts to Selenium Scripts.
  • Has knowledge of XPath and UI based testing through C, C++ and Python.
  • Experience of handling clients for two years, communicating timely results
  • Created manual and automation test cases through Python Selenium
  • Ability to do multitasking and self driven.

Education

Indraprastha Institute of Information Technology, Delhi

Master of Technology - MTech — Cyber Physical Systems

Aug 2022Jun 2024

Jaypee Institute Of Information Technology

Bachelor of Technology - BTech — ELECTRONICS AND COMMUNICATION ENGINEERING

Jan 2016Jan 2020

Jaypee Institute of Information Technology, Noida

Bachelor of Technology — ece

Jan 2016Jan 2020

Indraprastha Institute of Information Technology, Delhi

Master's Degree

Jaypee Institute of Information Technology

Bachelor's Degree

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