Naveen Batra

CEO

India20 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in memory compiler development across multiple technology nodes.
Proven track record in project management and team leadership.
Recognized for execution excellence with multiple awards.

Stackforce AI infers this person is a Semiconductor Design Architect with extensive experience in memory design and project management.

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Skills

Core Skills

Memory Compiler DevelopmentProject ManagementMemory DesignCustomer Support

Other Skills

Memory SpecificationsCustomer Interactions and SupportR&DCompiler DevelopmentProject LeadCircuit & Physical DesignQuality ChecksValidationsTeam BuildingAutomationMemory Specification DevelopmentsMemory Architecture EvaluationSchematic Design EntriesPhysical LayoutingExtraction

About

Memory Specifications, Customer Interactions and Support, New Fearures, R&D, Markering Needs, Compiler Developement, Project Lead, Cross Team Interactions, Circuit & Physical Design, Quality Checks, Validations, Team Building, Team Growth and Motivation. Enriched hands-on experience in: 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, 32nm, 45nm, 55nm, 90nm tech nodes on world's top 5 foundries. Finfets, Planar, Fdsoi. HS, HD, UHD, ROM, DP, PDP, SRAM, RF, LP, LL, split core, bank, page design architectures. Memory Compiler developement, validations and releases. Test chip and specific instance developements. Memory's test/debug modes, bist, atpg, scan chains, power down modes, redundancy, dual rail, write/read assist, body bias, bypass and other custom features design and validations. Platform common tasks, alligment, new design/features analysis, flows update, generic guidelines setup, cross reviews and support. Technology study, reliability and ageing analysis, OCV data analysis. Project planning & Team management. Training and Mentoring. Automation, methodology updates and flows developement. Customer's specific requests and Customer support. Personal: Hard working, self motivated, proactive, agile, good scriptor, analytic approach. undegone various industry standard training modules. Recieved team awards, individual perfomance awards, spot awards for almost all of the projects involved within. Appreciated for execution execellence.

Experience

20 yrs 10 mos

Total Experience

10 yrs 5 mos

Average Tenure

12 yrs 5 mos

Current Experience

Synopsys inc

5 roles

Architect

Feb 2025 – Present · 1 yr 4 mos

Memory Specifications, Customer Interactions and Support, New Fearures, R&D, Markering Needs, Compiler Developement, Project Lead, Cross Team Interactions, Circuit & Physical Design, Quality Checks, Validations, Team Building, Team Growth and Motivation.
Enriched hands-on experience in:
2nm, 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, 32nm, 45nm, 55nm, 90nm tech nodes on world's top 5 foundries.
Finfets, Planar, Fdsoi.
HS, HD, UHD, ROM, DP, PDP, SRAM, RF, LP, LL, split core, bank, page design architectures.
Memory Compiler developement, validations and releases.
Test chip and specific instance developements.
Memory's test/debug modes, bist, atpg, scan chains, power down modes, redundancy, dual rail, write/read assist, body bias, bypass and other custom features design and validations.
Technology study, reliability and ageing analysis, OCV data analysis.
Project planning & Team management.
Training and Mentoring.
Automation, methodology updates and flows developement.
Customer's specific requests and Customer support.
Personal: Hard working, self motivated, proactive, agile, good scriptor, analytic approach. undegone various industry standard training modules.
Recieved team awards, individual perfomance awards, spot awards for almost all of the projects involved within. Appreciated for execution execellence.

Memory SpecificationsCustomer Interactions and SupportR&DCompiler DevelopmentProject LeadCircuit & Physical Design+6

Senior Manager

Promoted

Nov 2021 – Feb 2025 · 3 yrs 3 mos

Memory Specifications, Customer Interactions and Support, New Fearures, R&D, Markering Needs, Compiler Developement, Project Lead, Cross Team Interactions, Circuit & Physical Design, Quality Checks, Validations, Team Building, Team Growth and Motivation.
Enriched hands-on experience in:
7nm, 10nm, 14nm, 16nm, 28nm, 32nm, 45nm, 55nm, 90nm tech nodes on world's top 5 foundries.
Finfets, Planar, Fdsoi.
HS, HD, UHD, ROM, DP, PDP, SRAM, RF, LP, LL, split core, bank, page design architectures.
Memory Compiler developement, validations and releases.
Test chip and specific instance developements.
Memory's test/debug modes, bist, atpg, scan chains, power down modes, redundancy, dual rail, write/read assist, body bias, bypass and other custom features design and validations.
Technology study, reliability and ageing analysis, OCV data analysis.
Project planning & Team management.
Training and Mentoring.
Automation, methodology updates and flows developement.
Customer's specific requests and Customer support.
Personal: Hard working, self motivated, proactive, agile, good scriptor, analytic approach. undegone various industry standard training modules.
Recieved team awards, individual perfomance awards, spot awards for almost all of the projects involved within. Appreciated for execution execellence.

Memory SpecificationsCustomer Interactions and SupportR&DCompiler DevelopmentProject LeadCircuit & Physical Design+6

Manager II

Promoted

Jun 2018 – Nov 2021 · 3 yrs 5 mos

Memory Specifications, Customer Interactions and Support, New Fearures, R&D, Markering Needs, Compiler Developement, Project Lead, Cross Team Interactions, Circuit & Physical Design, Quality Checks, Validations, Team Building, Team Growth and Motivation.
Enriched hands-on experience in:
7nm, 10nm, 14nm, 16nm, 28nm, 32nm, 45nm, 55nm, 90nm tech nodes on world's top 5 foundries.
Finfets, Planar, Fdsoi.
HS, HD, UHD, ROM, DP, PDP, SRAM, RF, LP, LL, split core, bank, page design architectures.
Memory Compiler developement, validations and releases.
Test chip and specific instance developements.
Memory's test/debug modes, bist, atpg, scan chains, power down modes, redundancy, dual rail, write/read assist, body bias, bypass and other custom features design and validations.
Technology study, reliability and ageing analysis, OCV data analysis.
Project planning & Team management.
Training and Mentoring.
Automation, methodology updates and flows developement.
Customer's specific requests and Customer support.
Personal: Hard working, self motivated, proactive, agile, good scriptor, analytic approach. undegone various industry standard training modules.
Recieved team awards, individual perfomance awards, spot awards for almost all of the projects involved within. Appreciated for execution execellence.

Memory SpecificationsCustomer Interactions and SupportR&DCompiler DevelopmentProject LeadCircuit & Physical Design+6

Staff Engineer

Jun 2017 – Jun 2018 · 1 yr

Senior Engineer II

Jan 2014 – Jun 2017 · 3 yrs 5 mos

St microelectronics

Engineering Specialist (tech), Memory Design

Aug 2005 – Jan 2014 · 8 yrs 5 mos

Memory Specification Developements, Memory Architecure Evaluation, Schematic Design Entries, Physical Layouting, Extraction, Design Validations(Memcell, Latch, Selftime, Senseamp, Poweron, Fullcut, Tight stimuli validations, Cdl Simulations), Memory Characterizations(Tim/Pow/Cap/Leak), Compiler Submissions, Customer supports

Memory Specification DevelopmentsMemory Architecture EvaluationSchematic Design EntriesPhysical LayoutingExtractionDesign Validations+5