Mar 2024 – Apr 2026 · 2 yrs 1 mo

• Led Backend activity of project with 5-member team. Work involved project execution planning & review,
• resource planning, Data management, responsible for receivables and deliverables across different domain.
• Work involved discussion with PLM & market team to assess the requirement of product in market. Product
• spec enhancement in-form of multiple protocol support.
• Worked closely with Analog (RF), Architect to assess DIE & device PIN requirement, Design and DFT to
• plan BE requirement and push PPAS goals.
• Work related to Package assessment like package type selection, ARC rule signoff, ESD signoff, STACK-
• DIE option validation and IO PAD finalization.
• Gained exposure of multiple chip protocols like SDIO, SDMMC, SPI, xSPI, UART, I2C, I2S, ADC.
• Have exposure to paper submission (5)/presentation in TI internal conferences.

Nov 2020 – Mar 2024 · 3 yrs 4 mos

• Responsible for full PD of WIFI-BLE platform ASIC end to end closure. Work includes floor-planning &
• memory type selection, PG resistance estimation, IO placement, CHIP PINOUT feedback generation,
• CTS spec generation, Clock-QOR optimization.
• Responsible for full PNR methodology creation of device. Work includes utilization enhancement, DIE area
• reduction, critical interface IO-MUXING feedback generation, Low Power technique designing, IR-drop
• handling, switch expansion strategy, IORING area utilization.
• Expertise in UPF designing for devices and consulted by different business unit for UPF in TI.
• Designed methodology to solve TI specific Low Power device problem by defining UPF construct. This
• further get adapted across different business unit in TI.
• Hands on experience of timing signoff closure technique and methodology development for DRV fixing,
• IO timing closure strategy, CAD Flow enhancement
• Involved in silicon debug, RF issue debug, Board level parameter and generating feedback from layout.

Dec 2018 – Nov 2020 · 1 yr 11 mos · Bengaluru, Karnataka, India

• Responsible for all aspects of Physical Design for Full-chip/Blocks covering Floor-planning, Budgeting, Clock Tree planning & analysis, Placement, Scan reordering/analysis, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
• Effective communicator to provide status of the progress with 2 weeks ahead than schedule.
• Completed PHYSICAL DESIGN/STA of SOC block with 82 memory & 2 PLLs, 1.8m instances, working at 400Mhz with 135k ports & (6000um*400um) aspect ratio in 7nm technology.
• Expertise in congestion analysis in placement. Develop guides for placement structure using categories blockages. Resolved SCANDEF issues which impact congestion.
• Expertise in SCAN reordering/analysis and successfully resolve the timing impact of SCANDEF ordered connection.
• Successfully completed SPINE CLOCK structure for further reduction of latency and skew.
• Designed and Automated power-plan flow for the project of CLOCK multi-height cells with no IR issues.
• Completed RDL routing of IOPAD, DECAP cell placement around PLL and power-plan over PLL.
• Successfully completed TESTCHIP TOP (mainly focused on physical verification and issues) with IO-PAD cell placement and RING power structure development in 8nm technology.

Jul 2017 – Dec 2018 · 1 yr 5 mos · Noida, Uttar Pradesh, India

• Responsible for full development of flow: Floor planning, Bus/Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
• Effective communicator to provide status of the progress, problem and solution to management and other engineers
• Participated in developing methodologies, flow automation and improvements on existing flows to increase productivity.
• Completed PHYSICAL DESIGN/STA of SOC block with 42 memory, 0.8m instances working at 1.4Ghz in 16nm technology.
• Successfully executed ECOs of two blocks with functional changes required during MTO. Derived manual clock path for bunch of flops for setup failure fix.
• Successfully build manual balance tree for CTS which combined H-TREE solution by Synopsys and MULTI-SOURCE TAP point locator with manual script.

Jan 2017 – Jun 2017 · 5 mos · Noida, Uttar Pradesh, India

• Trained in physical design/STA (Digital Networking) of SOC development team.
• Main work focused on clock tree synthesis during internship
• Familiar with industry standard CAD methodologies from Synopsys and/or Mentor
• Did many experiment, simulations, analysis on MICA simulator for mesh structure of CTS.
• Deliver methodology and design flows for simulator tool.

Jun 2015 – Jul 2015 · 1 mo · Noida, Uttar Pradesh, India

• Here, I learned about micro-controller and its coding. Did many ARDUINO based project.