Jan 2024 – Dec 2024 · 11 mos · Bengaluru, Karnataka, India · On-site

Aug 2022 – Dec 2023 · 1 yr 4 mos · Bengaluru, Karnataka, India

• Working on IP verification to validate DFT features.
• Verifying MBIST repair feature using BISR/BIRA. And dynamically configuring Fuses based on random fault injection.
• Bringing up IJTAG/JTAG BFMs in IP verification environment.
• IO Loopback BIST to verify TX-RX Buffer connectivity.
• HVQK/BI to verify and observe toggling activities.
• SCAN and MBIST Verification.
• Worked on Netlist generation, ICL extraction, patterns generation and verification.
• Generating patterns by adding proper TDR programming through PDLs and verify the different
• flavors for SCAN patterns using SCAN Proxy (Intest/Extest , EDT Bypass, Chain, scan_capture) for both stuckat and atspeed variants.
• Worked on OCC verification at RTL level to check clock behavior during S@ and @S testing.
• Worked on MBIST verification activities with Testmax SMS.

Jan 2021 – Aug 2022 · 1 yr 7 mos · Bengaluru, Karnataka, India · Hybrid

• Worked on SoC MBIST Insertion, SoC level Integration, Validation and Post-Si pattern delivery for ATE testing.
• MBIST implementation as per Design requirements.
• MBIST insertion based on Clock Grouping, Memory Type, Power-Domain and feedback from backend physical implementation.
• Generated and Validated MBIST Algorithms with HVM(Hign Volume Manufacturing) reset.
• UPF Validation to make sure components are in correct power domain as per Design requirements and no
• isolation and power domain crossing issues.
• GLS – Zero Delay/SDF simulations to make sure zero design bugs and no timing related issues.
• MBIST pattern Delivery for HVM/Manufacturing testing.

Sep 2015 – May 2019 · 3 yrs 8 mos · Bengaluru Area, India · On-site

• Worked on SoC Integration and Validation aspects for Scan Fabric and TAP Network.
• Implemented Scan Fabric and TAP network as per DFT requirement.
• Used mentor’s IJTAG (1687) tool to generate the basic tests to validate IJTAG Network using ICL and PDL.
• Implemented conversion script to generate ITPP test content from regular TAP IR/DR
• instructions which are generated from PDL.
• Worked on IP Verification aspects.
• Worked on custom BFM implantations and helped SoC teams to integrate in SoC Verification Environment.
• Created RDL (Register Description Language) files and generated RAL classes to validate front-door and back-door access of registers.
• Modify/add direct/random/constrained-random test cases to analyze the RTL and find issues in the Design and debug failures.

Jun 2014 – Jun 2015 · 1 yr · Bangalore · On-site

• Implemented Module Based trackers for multiple IPs to ease debug process for muti-instance components in SOC.
• Implemented Conversion script to generate Register Description Language (RDL) and Functional Coverage file from XLS input by using Perl.
• Implemented regression filter script which extract Error signatures from test regression area and sends detailed status report to IP owners.
• Created standalone Scan/TAP Fabrics to speed up DFT design implementation and validation.
• Helped/Worked on IP Verification aspects.

May 2019 – Jan 2021 · 1 yr 8 mos · India · On-site

• Worked on IP Verification activities.
• Worked on IEEE1500 protocol to verify TestMAX Access IP.
• Worked on AMBA(AXI4) to verify TestMAX SLT IP.
• Worked on integration aspects of TestMAX SLT IP with USB environment to transport DFT content (Scan/TAP) over High-speed interfaces (USB).