CHANDAN JHA — Software Engineer
=> work with microarchitecture, pipeline stages, clock domains implementation and sign off => Implementing end to end:- -> CPU Hardware accelerator Architecture, -> PNR Implementation Feasibility & PPA tradeoff, -> Power analysis and tech node trade off -> Floorplan, Place, CTS, Route, PRO & Sign-off, -> Timing closure: Setup, Hold, MMMC, BTO/MTO -> cross corner, custom ip check, skew check -> STA: Front-end to back-end Sta sign-off -> Constraint methodology: SDC authoring -> Cross-stage correlation, waiver analysis -> ECO flows: hold/setup/leakage/TDRC closure
Stackforce AI infers this person is a VLSI Hardware Engineer with expertise in CPU architecture and physical design.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 9 mos
Skills
- Physical Design
- Microarchitecture
Career Highlights
- Expert in CPU Microarchitecture and Physical Design.
- Proficient in Timing Signoff and Constraints Management.
- Strong background in VLSI Design and Hardware Engineering.
Work Experience
Qualcomm
Senior Hardware Engineer (8 mos)
Hardware Engineer (3 yrs 2 mos)
Western Digital
SOC Verification Intern (6 mos)
WISDOM360
PHYSICS [K-12] Program (1 yr 11 mos)
Education
Master of Technology - MTech at National Institute of Technology Karnataka
Bachelor of Technology - BTech at SHRI RAMSWAROOP MEMORIAL UNIVERSITY
SCHOOL at Govt. Boys Senior Secondary School, NO-1 Badarpur New Delhi
