Gaurav Gupta

Director of Engineering

Noida, Uttar Pradesh, India22 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 21 years of VLSI design experience.
Expert in timing analysis and signoff.
Proven leadership in multicultural environments.

Stackforce AI infers this person is a VLSI Design Expert with extensive experience in Hardware Engineering and ASIC development.

Contact

Skills

Core Skills

Hardware EngineeringDesign ManagementStatic Timing Analysis

Other Skills

Backend ImplementationPCIeCXLUCIeRTLAFrontend SynthesisDataflow based FloorplanFusion CompilerConstraints generationLogical Equivalence checkingTiming Signoff methodologiesTiming constraints developmentTiming analysisDFTPnR

About

More than 21 years of VLSI design industry experience with various MNCs. Specialties: • Generation and development of timing constraints for multiple clock domains and generated clocks, post-layout constraints development for timing closure. • IP level constraints integration, Timing analysis and signoff for tapeout activities. • Full chip STA signoff. • Design issues debug like lint, elab, clock domain crossing (CDC), datapath pipe-lining requirement. • Full chip low power synthesis, Debug of synthesis issues & other netlist quality checks. • Formal equivalence between RTL Vs netlist and netlist Vs netlist; Functional ECOs implementation. Working Experience of: • Execution model of multicultural working environment. • Technical activities coordination. • Discussion with Frontend design teams and timing critical issues resolution. • Constraints review and feedback. • DFT, P&R, clock tree implementation and GLS support. • Automotive safety critical ASIL-D NoC/System level NoC constraints management and backend implementation. • Arteris FlexNoC & Piano integration for faster Timing closure. • Improvement of timing convergence process for faster timing closure. Tools: Design Compiler, Prime Time, Formality, Innovus.

Experience

22 yrs 1 mo

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs 4 mos

Current Experience

Synopsys inc

2 roles

Director, ASIC Digital Design

Promoted

May 2026 – Present · 1 mo · Noida · On-site

Managing the Backend Implementation of PCIe/CXL Controller Subsystem Team.

Backend ImplementationPCIeCXLHardware EngineeringDesign Management

Sr. Manager, ASIC Digital Design

Jan 2022 – Apr 2026 · 4 yrs 3 mos · Noida · On-site

Managing the Backend Implementation of PCIe/CXL/UCIe and providing guidance to several other Digital IPs for,
1) sub-system partitioning through RTLA tool & based on design functionality.
2) Frontend Synthesis for early detection for issues.
3) Dataflow based Floorplan guidance for internal & external consumption.
4) Fusion Compiler PnR implementation.
5) Constraints generation & TCM based validation, demotion.
6) Logical Equivalence checking and improvement in RTL code for faster turnaround time.
7) Timing Signoff methodologies for different foundries and technology nodes.
8) Backend Flow maturity for complex nodes like TSMC 3nm Hybrid & SFx4.
Alongside managing small part of IP verification team to implement new features.

Backend ImplementationPCIeCXLUCIeRTLAFrontend Synthesis+7

Intel corporation

SoC Design Engineer

Dec 2020 – Jan 2022 · 1 yr 1 mo · Bangalore Urban, Karnataka, India

SoC Full-Chip Timing Lead, Discrete Graphics SoC, Intel Corporation
Responsible for :
1) Fullchip and block level constraints development.
2) Discussion with Frontend Integration & IP teams for critical timing issue resolution.
3) Timing analysis & guidance to PnR teams for resolution of timing issues.
4) Interaction with DFT teams for implementation of DFT modes and timing related feedbacks.

Timing constraints developmentTiming analysisDFTPnRStatic Timing AnalysisHardware Engineering

Stmicroelectronics

Sr. Staff Engineer

Jun 2017 – Dec 2020 · 3 yrs 6 mos · Greater Noida

Professional Experience:
Physical design experience in working with advanced process technology nodes.
Knowledge of entire spectrum of RTL2GDSII (FE to BE) flow
i.e. Synthesis, Floorplan development, Placement, CTS, Routing, STA, Electrical signoff, Power-Analysis, Formal Verification etc.
Working experience on Multiple clock domain (System/Aux) designs.
Synth/HandOff/SignOff & PostLayout Netlist/Low Power checks development.
Working experience of synthesis and constraints development.
Abstraction model generation expertise like ILM/ETM.
Pre-layout and post-layout timing analysis and Clock Tree synthesis guidance.
DMSA/Manual timing fixing and custom scripting for timing fixes and leakage recovery.
Clock & Reset tree structures tracing, checks and familiarity with backend implementation issues.
Good understanding of library, derates, AOCV/POCV and intricate dependency on timing analysis.
Experience on programing in TCL, Perl and others.
Familiar with Bus protocols like AMBA AXI/AHB, APB for backend implementation.
Familiar with front end flows - Lint, cross domain crossing checks (CDC).
Familiar with Low power design concepts.
Familiar with DFT concepts.
Familiar with circuit SPICE modeling.

Physical designRTL2GDSII flowSynthesisTiming analysisLow Power checksHardware Engineering

Nxp acquires freescale semiconductor

3 roles

Staff Design Engineer

Oct 2014 – Jun 2017 · 2 yrs 8 mos

Synthesis/STA hands-on expertise on full Chip & multiple blocks from 10+ successful SoC tape-outs on various technologies ranging from 180nm to 28nm.
Design partitioning, Logic/Physical synthesis, DFT SCAN insertion for ATPG/LBIST, LEC/Formal verification.
Functional ECO implementation with manual ECOs/Scripting & using Conformal ECO.
Block level Static Timing Analysis (STA) closure for different modes with functional/timing ECO implementation and generation.
Manual and Automatic Timing ECO generation for setup/hold fixing and leakage reduction techniques using GBA/PBA approach.
Responsibilities:
Technology node analysis in terms of standard cell DDK quality.
Timing and power analysis for new technology adoption; Worst case scenario analysis for timing and leakage power.
synthesis, scan insertion and STA closure.
Environment creation for scan insertion in synthesized N/L.
Developing scripts for automating the flow where needed.
Ensure the block should be timing clean.
Performing Static Timing Analysis at block level and fix violations, timing budgeting.
Tools:
RTL Compiler, Conformal LEC, ETS/Tempus, Virtuoso, Spice simulator.
Languages:
Decent scripting and debugging skills in Shell/C-Shell.
Advanced level Tcl & Perl scripting. Prepared Automated Metric and Quality check flow for Synthesis sign-off.

SynthesisSTALECECO implementationTiming analysisHardware Engineering

Lead Design Engineer

Jul 2012 – Sep 2014 · 2 yrs 2 mos

Synthesis/Formal verification at block and chip_top level.
Timing constraints generation and timing sign-off.
Timing convergence using high speed design techniques with signal integrity.
Good understanding of static timing analysis (STA) and sign-off flows.
Hands-on experience with Low power design techniques.

SynthesisTiming constraints generationLow power designHardware Engineering

Sr. Design Engineer

Oct 2007 – Jun 2012 · 4 yrs 8 mos

Synthesis/Formal verification at block and chip_top level.
Timing convergence using high speed design techniques with signal integrity.
Good understanding of static timing analysis (STA) and sign-off flows.
Hands-on experience with Low power design techniques.

SynthesisTiming constraints generationLow power designHardware Engineering

Virage logic

2 roles

Engineer

Promoted

Oct 2006 – Oct 2007 · 1 yr

Standard cell library development, characterization, View generation and library validation on Cadence/Synopsys/Magma place and route flow.
SRAM Memory compiler development and its optimization for timing and power.

Library developmentCharacterizationValidation

Assistant Engineer

Dec 2004 – Sep 2006 · 1 yr 9 mos

Validation of high speed and ultra high density standard cell libraries.

Jsr instruments

Associate Design Engineer

Aug 2003 – Jul 2004 · 11 mos

Embedded Systems hardware Design based on 8bit / 16bit microcontrollers.
software writing in assmebly and C/C++ to run the microcontroller based systems.

Embedded SystemsC/C++