Yash Kant

Product Engineer

Noida, Uttar Pradesh, India6 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over five years of experience in memory design engineering.
Expertise in SRAM, ROM, and Register Files compilers.
Proven track record in PPA optimization and variation analysis.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in memory design and optimization.

Contact

Skills

Core Skills

Variation AnalysisSramQuality AssuranceTelecommunications

Other Skills

Shell ScriptingCircuit DesignLinuxMonte CarloHspiceDesign EngineeringDigital Circuit DesignVerilogUnixTransistorsCommunication ProtocolsRouting ProtocolsCharging SystemsMicrosoft WordNetwork Architecture

About

As a Staff Engineer R&D at Synopsys Inc, I bring over five years of experience in memory design engineering, specializing in SRAM, ROM, and Register Files compilers. My expertise includes read and write path optimization, debugging critical margins, and conducting comprehensive variation analysis to enhance power, performance, and area (PPA). My work has involved end-to-end cycle involvement in memory compiler development and PPA optimized instance releases.

Experience

6 yrs 7 mos

Total Experience

3 yrs 3 mos

Average Tenure

4 yrs 10 mos

Current Experience

Synopsys inc

4 roles

Staff Engineer R&D

Promoted

May 2026 – Present · 1 mo

Senior Engineer R&D

Promoted

Jan 2024 – Apr 2026 · 2 yrs 3 mos

Presently i am working as a Senior Memory Design Engineer.
My work includes read and write path optimization, debugging and fixing critical margins, QAs , trend checks, PPPA optimization.
Involvement in the compiler's (SRAM, Register Files, ROM) end to end cycle.

Shell ScriptingVariation AnalysisCircuit DesignLinuxMonte CarloHspice+3

R&D Engineer I

Jun 2021 – Dec 2023 · 2 yrs 6 mos

I worked as a Memory Design Engineer.
My work includes verification and fixation of different memory compilers QAs.
Read Margin and Write Margin analysis and fixes.

Variation AnalysisCircuit DesignVerilogUnixHspiceTransistors+2

Post Graduate Engineer Trainee

Jan 2021 – May 2021 · 4 mos

I was an intern here during my fourth semester of M.Tech.
I gained knowledge about HSPICE, Monte-Carlo Analysis, Process Entitlement, Bitcell Analysis, and its various figures of merit (SNM, WM, Read Current, Leakage).

Reliance jio

Deputy Manager

Jun 2015 – Mar 2017 · 1 yr 9 mos · Navi Mumbai, Maharashtra, India · On-site

I had worked with Reliance Jio Infocomm Limited for nearly 2 years. Here I learned and gained an insight into the telecom core domains that encompass VoIP, IMS, FTTX, and WiFi.
My responsibilities here were
1) Quality assurance and validation of scenarios as per usages to cash flow process (rating, charging, and billing).
2) Monitoring the performance, quality, and efficiency of the charging system (SAP OCS).
3) Protocol (DIAMETER, RADIUS. SOAP & SIP) analysis on Ro, Sy, and Gy interfaces.
4) Analysis of call flow requests, responses, and updates with tracing tools.
5) Designing and implementation of the test cases as per the usages to cash flow.
6) Coordinating with business and development teams in the integration, testing, and commercialization of products.

Shell ScriptingCommunication ProtocolsRouting ProtocolsQuality AssuranceCharging SystemsMicrosoft Word+7

Defence research and development organisation (drdo)

Summer Internship

Jun 2013 – Jul 2013 · 1 mo · New Delhi, Delhi, India

Learned about “Line of Sight and Radio Propagation”.
Learned how to determine the line of sight of communication for mapping out and developing the communication facilities in terrain areas.