Satyajit Desai

Software Engineer

Bengaluru, Karnataka, India9 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 9 years of experience in VLSI design.
Authored 20+ technical articles for knowledge sharing.
Led successful deployment of advanced PrimeTime features.

Stackforce AI infers this person is a VLSI Design and Static Timing Analysis expert in the semiconductor industry.

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Skills

Core Skills

Static Timing AnalysisVlsi Design

Other Skills

Simultaneous Multi-Corner AnalysisTiming Constraint ManagerHyperScaleIR-STAPrimeTimeCycle-dependent uncertaintyParasitic ExplorerPhysical design implementationECOFloor planningClock tree synthesisPlace and routePhysical verificationDMSAICC2

About

As a Staff STA Engineer at Synopsys Inc, I bring over 9 years of experience in VLSI design and static timing analysis. My work experience focuses on full chip timing convergence and deploying of advanced PrimeTime features such as SMVA, HyperScale, IR-STA and Timing Constraint Manager TCM-SDC Lint across multiple accounts. I have authored over 20 SolvNetPlus articles, contributing to knowledge sharing and technical insights at Synopsys. My key contributions include leading the deployment of the cycle-dependent uncertainty feature in production, culminating in a successful tape-out and a presentation at SNUG 2025 Bangalore. I am motivated by opportunities to drive innovation in VLSI design and static timing analysis. I am dedicated to advancing semiconductor design by delivering results through collaboration and technical proficiency.

Experience

9 yrs 11 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 11 mos

Current Experience

Synopsys inc

Staff STA Engineer

Jul 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Worked on Simultaneous Multi-Corner Analysis (SMC), Timing Constraint Manager (TCM) SDC Lint, B2T check, HyperScale, IR-STA & PT-ECO freeze silicon features and successfully deployed new PrimeTime features across multiple accounts.
Authored over 20 SolvNetPlus articles covering a broad range of PrimeTime topics as part of a knowledge sharing initiative at Synopsys.
Took ownership of the cycle dependent uncertainty feature and successfully deployed it in production runs. Achieved successful tape out with the cycle dependent uncertainty feature and presented it at SNUG 2025 Bangalore.
Collaborated closely with the PrimeTime R&D team to develop the SMVA HyperXdomain, MPW and save_session common data sharing features to meet the key requirements. I understood the company's needs and worked alongside the PrimeTime R&D team to deliver the key requirements, then partnered with the customer CAD team to enable production usage.
Worked closely with the CAD and STARRC teams to integrate the Parasitic Explorer feature within PrimeTime interface. Delivered the capability for post silicon debug and achieved reduced TAT with single user interface.
Performed Interconnect Skew Analysis (ISA), Voltage Slack Analysis (VSA) and Design Variation Analysis (DVA) on customer database for showcasing new features of PrimeShield.

Simultaneous Multi-Corner AnalysisTiming Constraint ManagerHyperScaleIR-STAPrimeTimeCycle-dependent uncertainty+3

Insemi technology services pvt. ltd.

Physical Design and STA Engineer

Nov 2018 – Jul 2022 · 3 yrs 8 mos · Bengaluru, Karnataka, India · On-site

Worked on Physical design implementation and STA timing closure of DDR IPs.
Hands on Experience in broad aspects of VLSI design including floor planning, clock tree synthesis, place and route, static timing analysis and physical verification.
Worked with large designs (~500M) with frequencies more than 2 GHZ on 3nm - 28nm technology nodes with EDA tools such as IC Compiler 2, PrimeTime, PrimeShield, Formality, IC Validator and Calibre.
Achieved Full Chip timing closures with signal integrity analysis, performed signoff constraint checks such as Galaxy Constraint Analyzer (GCA) check, clock domain crossing (CDC) checks and PTPX signoff power analysis.
Writing and implementing ECO’s for full chip timing convergence by running chip top level and block level STA in MCMM & PT DMSA environment.
Performing logical equivalence-checks, DRC clean up, Layout Versus Schematic (LVS), and sign-off checks to achieve targeted PPA goals.
Worked on different ASIC design CAD flows such as Synopsys Makefile based, AMD TileBuilder based flows.

Physical design implementationStatic Timing AnalysisECOFloor planningClock tree synthesisPlace and route+2