Ujjwal Talati

Director of Engineering

Ahmedabad, Gujarat, India13 yrs 8 mos experience

Highly Stable

Key Highlights

Proven leadership in ASIC digital design management.
Strong expertise in FPGA and VLSI technologies.
Top academic performer with a 9.53 CGPA.

Stackforce AI infers this person is a highly skilled ASIC and FPGA design engineer with leadership experience in semiconductor technology.

Contact

Skills

Other Skills

AlgorithmsElectronicsCVerilogSystem VerilogFPGA prototypingVHDLC++Embedded SystemsLogic DesignPspiceMatlabModelSimVLSIFPGA

Experience

13 yrs 8 mos

Total Experience

5 yrs 3 mos

Average Tenure

3 yrs 1 mo

Current Experience

Synopsys inc

2 roles

ASIC Digital Design, Manager

Promoted

Jan 2024 – Present · 2 yrs 5 mos · Pune, Maharashtra, India · On-site

ASIC Digital Design Engr, Staff

Apr 2023 – Dec 2023 · 8 mos · Pune, Maharashtra, India · On-site

Softnautics

2 roles

Associate Principal Engineer

Promoted

Aug 2018 – Apr 2023 · 4 yrs 8 mos · Ahmedabad Area, India

Senior Digital Design Engineer

Sep 2016 – Aug 2018 · 1 yr 11 mos · Ahmedabad Area, India

Previously Known as Sibridge Technologies Pvt. Ltd.

Sibridge technologies

Digital Design Engineer: IP Group

Aug 2012 – Aug 2016 · 4 yrs · Ahmedabad Area, India

Isro - indian space research organization

Research Intern: Space Application Center

Jan 2012 – Jul 2012 · 6 mos · Ahmedabad Area, India

Education

Gujarat Technological University

B.E — Electronics & Communication Engineering

Jan 2008 – Jan 2012

Best High/Higher Secondary School

Jan 2006 – Jan 2008

Stackforce found 100+ more professionals with Algorithms & Electronics

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