학현 이

Software Engineer

Seoul, South Korea6 yrs 1 mo experience

Key Highlights

Expert in Static Timing Analysis and Physical Implementation.
Proficient in Python for automation and scripting.
Strong background in semiconductor design and verification.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with expertise in Physical Implementation and Timing Analysis.

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Skills

Core Skills

Physical ImplementationPythonStatic Timing AnalysisDesign Constraints

Other Skills

Physical Implementation script managementSynthesis workflow frameworkFusion-Compiler maintenanceSanity check managementSTATCLTiming analysisECO script releaseMagillemSDCSpyglass엔지니어링베릴로그RTL 디자인

Experience

6 yrs 1 mo

Total Experience

2 yrs 1 mo

Average Tenure

1 yr 10 mos

Current Experience

삼성전자

엔지니어

Aug 2024 – Present · 1 yr 10 mos · On-site

Synopsys inc

2 roles

Sr Engineer

Jan 2024 – Jul 2024 · 6 mos

Physical Implementation script management (23.10~)
Synthesis workflow framework build with python
Fusion-Compiler environment maintenance
Sanity check management script build

Physical Implementation script managementSynthesis workflow frameworkPythonFusion-Compiler maintenanceSanity check managementPhysical Implementation

SOC 1

Mar 2022 – Dec 2023 · 1 yr 9 mos

CHIP TOP STA (22.10~23.09)
HyperScale flow release for sub block engineer increased ECO performance
Build STA report script environments with python pandas library and release to engineer for fast analysis.
Correlation check between Top level and sub block level timing with python
ECO script release to sub-block engineer for interface timing.
Make MTO checklist parsing script with python.
SUB TOP STA (22.03~22.10)
Block timing analysis and timing eco
Fusion Compiler synthesis to initial place
Make timing analysis script about block boundary flip-flop with TCL in Primetime

STAPythonTCLTiming analysisECO script releaseStatic Timing Analysis

Coasia nexell

Engineer

Jan 2020 – Jan 2022 · 2 yrs

(20.11~22.01)
CHIP TOP integration with Magillem
CHIP TOP sanity check (Lint, VCLP)
Write Synopsys Design Constraints (SDC)
CHIP TOP level pre level Static Timing Analysis (STA) and Galaxy Constraint Analyzer (GCA) check.
FlexNoC performance exploration environment builds and measure with customer pattern.
PMU design with Cortex-A55 and verification with ARM DSM.
PMU sanity check (Spyglass Lint, DFT, CDC)
(20.04~20.11)
Power Management Unit (PMU) design and verification with TCL
PMU sanity check (Spyglass Lint, DFT, CDC)
PMU Synthesis with Design Compiler
PMU STA with Primetime