Zeel Makadia

Product Engineer

Ahmedabad, Gujarat, India0 mo experience

Key Highlights

Proficient in both Digital and Analog Circuit Design.
Hands-on experience with EDA tools and ASIC design flow.
Strong foundation in VLSI design principles.

Stackforce AI infers this person is a VLSI Design Intern with a focus on Digital and Analog Circuit Design.

Contact

Skills

Core Skills

Digital Circuit DesignAnalog Integrated Circuit DesignVhdlSystem VerilogVerilogAsic

Other Skills

ADCEDA Tool ExperienceAnalog Circuit DesignLayout DesignPhysical DesignAnalog CircuitsReliabilityProduct EngineeringDigital DesignsRTL DesignRTL CodingFinfetFunctional VerificationTesting of Digital Circuits

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Intel

Standard Cell Design Intern

May 2026 – Present · 1 mo · Bengaluru · On-site

Digital Circuit DesignAnalog Integrated Circuit Design

Synopsys inc

PE team intern

Feb 2024 – Apr 2025 · 1 yr 2 mos · Noida, Uttar Pradesh, India · On-site

VHDLSystem Verilog

Institute of plasma research

Winter Intern

Jan 2024 – Feb 2024 · 1 mo · Gandhinagar, Gujarat, India · On-site

. modules like ADC, 8B/10B encoder-decoder, and Serialisation-deserialisation Modules designed in Verilog.We also learned the techniques for enhance the performance of ADC.

ADCVerilog

Einfochips (an arrow company)

Summer Intern

Jun 2023 – Jul 2023 · 1 mo · Ahmedabad, Gujarat, India · Hybrid

I have worked in the E-infochips as a summer intern. during my internship period we have given task based on the FINFET transistor and ASIC design flow. after completion of the understanding of the ASIC design flow we have given the task on designing of digital circuit on Open-road EDA tool. it is a open Source EDA tool. We designed 4-bit Full Adder and completed the RTL to GDS II file Full Flow.

ASICEDA Tool Experience