Stylianos Antonios Balalis

Software Engineer

Sunnyvale, California, United States7 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Digital IC Design and Project Management.
  • Proficient in Verilog and Digital Design Synthesis.
  • Strong background in Formal Verification techniques.
Stackforce AI infers this person is a Digital IC Design Engineer with expertise in ASIC design and verification.

Contact

LinkedIn

Skills

Core Skills

Digital Ic DesignProject ManagementDigital Design Synthesis

Other Skills

VerilogFormal Verification (LEC)Architectural DesignPhysical DesignComputer-Aided Design (CAD)Project Leadership

Experience

7 yrs
Total Experience
3 yrs 6 mos
Average Tenure
5 yrs 7 mos
Current Experience

Synopsys inc

3 roles

Staff ASIC Digital Design Engineer

Feb 2024 – Present · 2 yrs 4 mos

VerilogProject ManagementDigital IC Design

Sr. ASIC Digital Design Engineer

Promoted

Aug 2023 – Feb 2024 · 6 mos

ASIC Digital Design Engineer

Nov 2020 – Aug 2023 · 2 yrs 9 mos

Digital Design SynthesisFormal Verification (LEC)

Moortec semiconductor limited

3 roles

Junior Digital Design Engineer

Sep 2019 – Nov 2020 · 1 yr 2 mos

Digital Design SynthesisFormal Verification (LEC)

Junior Digital Engineer

Jun 2019 – Sep 2019 · 3 mos

Digital Design SynthesisFormal Verification (LEC)

Junior Engineer

Jun 2018 – Sep 2018 · 3 mos · Greater Plymouth Area

Digital Design SynthesisFormal Verification (LEC)

Education

University of Southampton

Bachelor's degree — Electronic Engineering

Jan 2016 – Jan 2020

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