Satik Asatryan

Design Manager

Charentsavan, Kotayk Province, Armenia12 yrs 11 mos experience
Highly Stable

Key Highlights

  • Experienced in leading memory layout teams.
  • Expert in VLSI design and verification.
  • Proficient in creating layout methodologies.
Stackforce AI infers this person is a VLSI Design Engineer specializing in semiconductor layout design.

Contact

LinkedIn

Skills

Core Skills

VlsiPhysical DesignLayout Design

Other Skills

SemiconductorsDRCLVSFinFetCMOSSynopsys toolsIR-drop analysisASICMemory Layout methodologyTechnical documentationVerificationAnalog designIO devicesSchematic DesignXara

Experience

12 yrs 11 mos
Total Experience
12 yrs 11 mos
Average Tenure
12 yrs 11 mos
Current Experience

Synopsys inc

5 roles

Layout Design, Manager

Promoted

Jun 2019 – Present · 7 yrs · Армения

  • Leadership of memory layout team and projects
  • Layout design and verification of SRAM embedded memories
  • Memory Layout methodology and checks creation
  • Management of the layout team and projects, full technical support
  • Projects and resource planning
  • Performance reviews for team members
  • Trainings and technical documentation creation
  • Actively cooperating with Design and Compiler engineers
  • Memory quality checks creation and automation
VLSISemiconductorsDRCLVSFinFetCMOS+4

A&MS Layout Design Engr Sr1

Promoted

Jun 2016 – Jun 2018 · 2 yrs · Ереван, Армения

  • Layout design and verification
  • Layout design and verification for SRAM Embedded memory from simple leafcells to the top level
  • Project leading
VLSISemiconductorsDRCLVSFinFetCMOS+3

R&D Engineer II

Promoted

Jun 2014 – Jun 2016 · 2 yrs · Ереван, Армения

  • Layout design and verification
  • Layout design and verification of Analog desing and IO devices
  • DRC/LVS, ERC, Antenna, Lefcheck verifications
  • Extraction using StarRC
  • PWRA fixes
VLSIDRCLVSAnalog designIO devicesLayout design

R&D Engineer I

Nov 2012 – Jun 2014 · 1 yr 7 mos · Ереван, Армения

  • Leafcells development
  • DRC/LVS verification
  • Extraction
  • PWRA fixes
  • Instance level verifications
VLSIDRCLVSLayout design

Intern

Jul 2012 – Nov 2012 · 4 mos · Ереван, Армения

  • Schematic Design
  • Pre-layout simulations
  • Layout Design
  • DRC/LVS verification
  • Post layout simulations
Schematic DesignDRCLVS

Education

NATIONAL POLYTECHNIC UNIVERSITY OF ARMENIA

Master's degree — VLSI Design Engineer

Jan 2008 – Jan 2014

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