Kai Ge Yang

Software Engineer

Greater Toronto Area, Canada10 yrs 7 mos experience
Highly Stable

Key Highlights

  • Over 10 years in semiconductor industry.
  • Expert in Analog Mixed Signal Design.
  • Proven track record in high-speed SerDes development.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog Mixed Signal and high-speed interface technologies.

Contact

LinkedIn

Skills

Core Skills

Analog Mixed Signal DesignSerdes

Other Skills

Die-to-Die InterfaceTX DAC/DriverPAM4 SerDesClocking & CalibrationMulti-Protocol PCIeCalibrationCustom high-speed standard cell developmentEMIR simulationlayout optimizationPAM4 analog SerDesStandard Cell DevelopmentSAR ADC designcircuit designsimulation & verificationcustom layout

About

10+ years of experience in the semiconductor industry, Die-to-Die Interface & 224Gbps PAM4 SerDes

Experience

10 yrs 7 mos
Total Experience
3 yrs
Average Tenure
1 yr 5 mos
Current Experience

Marvell technology

Senior Staff Analog Design Engineer

Jan 2025 – Present · 1 yr 5 mos · Toronto, Ontario, Canada

  • Die-to-Die Interface
Die-to-Die InterfaceAnalog Mixed Signal Design

Synopsys inc

3 roles

Staff Analog Design Engineer

Jan 2024 – Jan 2025 · 1 yr · Greater Toronto Area, Canada

  • Novel TX DAC/Driver with 1/8 rate clock for 224Gb/s PAM4 SerDes in TSMC N5/N3, and Intel 18A
  • (ISSCC 2024, 7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS)
  • Clocking & Calibration for 128Gb/s Multi-Protocol PCIe7 & 64Gb/s PCIe6 SerDes in N5
TX DAC/DriverPAM4 SerDesClocking & CalibrationMulti-Protocol PCIeAnalog Mixed Signal DesignSerDes

Senior II Analog Design Engineer

Jan 2023 – Dec 2023 · 11 mos · Greater Toronto Area, Canada

Senior I Analog Design Engineer

Sep 2020 – Dec 2022 · 2 yrs 3 mos · Greater Toronto Area, Canada

Intel corporation

Design Engineer

Jan 2017 – Sep 2020 · 3 yrs 8 mos · Toronto, Ontario, Canada

  • Custom high-speed standard cell development in Intel 7nm
  • EMIR simulation and layout optimization on DFE and clocking for 58G PAM4 analog SerDes in Intel 10nm
Custom high-speed standard cell developmentEMIR simulationlayout optimizationPAM4 analog SerDesAnalog Mixed Signal Design

Envirosen inc

Analog/Mixed-Signal Design Engineer

Aug 2015 – Dec 2016 · 1 yr 4 mos · Greater Toronto Area, Canada

  • 12-bit 1MS/s SAR ADC design for CMOS image sensor from scratch to silicon success
  • Circuit design, simulation & verification, custom layout & post-layout optimization, Verilog RTL design & Verilog-A behavioural modelling
SAR ADC designcircuit designsimulation & verificationcustom layoutAnalog Mixed Signal Design

Amd

PEY Intern

May 2013 – Aug 2014 · 1 yr 3 mos · Greater Toronto Area, Canada

  • Circuit simulation, timing lib generation and Static Timing Analysis for DisplayPort-AUX/I2C, ClockStretcher, DroopDetector
  • Nominated for Intern of the Year
Circuit simulationStatic Timing AnalysisAnalog Mixed Signal Design

Education

University of Toronto

Bachelor of Applied Science (B.A.Sc.) — Electrical and Computer Engineering

Jan 2010 – Jan 2015

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