Saikrishna Siripuram

Product Manager

Hyderabad, Telangana, India7 yrs experience

Most Likely To Switch

Key Highlights

Expert in advanced analog layout design methodologies.
Proficient in multiple EDA tools and protocols.
Strong foundation in Electrical and Electronics Engineering.

Stackforce AI infers this person is a highly skilled Analog Layout Engineer with expertise in EDA tools and semiconductor protocols.

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Skills

Core Skills

Cadence Virtuoso Layout EditorCustom Compiler

Other Skills

PERCUnixPerlTCLCadence skillUSB2/3/4PCIE2/3/4VSR(128G)XSR(128G)eUSBMIPIMultipritocol SERDESSynopsys Custom CompilerCadence release flow(CHECK IT)Synopsys release flow(HIPRE)

About

Expertise in Rx,Tx,Macro level ESD and PLL(RO,LC). Familiar nodes: TSMC3 ,TSMC5,TSMC7,TSMC28 SAMSUNG 4, SAMSUNG 5 GF12,GF14,GF22FDSOI Intel18A,Intel18AP,Intel3 Protocols worked on: USB2/3/4,PCIE2/3/4,VSR(128G),XSR(128G),eUSB,MIPI,Multipritocol SERDES. Familiar with Synopsys Custom Compiler and Cadence virtuoso. Familiar with Cadence release flow(CHECK IT) and Synopsys release flow(HIPRE). Expertise in defining methodology for new tech nodes.

Experience

7 yrs

Total Experience

1 yr 9 mos

Average Tenure

1 yr 9 mos

Current Experience

Cadence design systems

Lead Design Engineer

Sep 2024 – Present · 1 yr 9 mos · Hyderabad, Telangana, India · On-site

PERCCustom compilerCadence Virtuoso Layout EditorUnixPerlTCL+1

Synopsys inc

3 roles

Senior Engineer

Promoted

Feb 2024 – Sep 2024 · 7 mos · Hyderabad, Telangana, India

A&MS Layout Design Engr II

Feb 2023 – Feb 2024 · 1 yr · Hyderabad, Telangana, India

A&MS Layout Design Engr,I

Feb 2022 – Feb 2023 · 1 yr · Hyderabad, Telangana, India

Invecas

2 roles

AMS layout Engineer I

Nov 2020 – Feb 2022 · 1 yr 3 mos · Hyderabad, Telangana, India

AMS Layout Engineer Trainee

Nov 2019 – Nov 2020 · 1 yr · Hyderabad, Telangana, India

Veda iit

Analog Layout Engineer trainee

May 2019 – Oct 2019 · 5 mos · Hyderabad Area, India

Completed training on Performing various kinds of analog layouts in Cadence Virtuoso layout editor(28nm,22nm ), implementations from top-level, floor planning down to complex block level layouts
Knowledge of various analog layout techniques, understanding of various circuit principles as affected by layout such as speed, capacitance, power, noise and area.Good matching for critical transistors.
DRC/LVS/Antenna/LPE , CMOS Device Physics, CMOS/FinFET Fabrication Knowledge.A good programming skills in UNIX,PERL,TCL