Priyank Shukla

Product Manager

Mississauga, Ontario, Canada18 yrs 9 mos experience

Highly Stable

Key Highlights

Leader in high-speed interconnect IP for AI and HPC systems.
Key contributor to emerging standards in semiconductor technology.
Experienced in managing complex product portfolios.

Stackforce AI infers this person is a leader in semiconductor technology and high-performance computing.

Contact

Skills

Core Skills

High-speed SerdesHigh Performance ComputingEthernetAnalog Mixed Signal DesignHigh Speed SerdesTechnical SupportAnalog DesignVoltage Regulator Design

Other Skills

SoCSpecification DevelopmentSerDes DesignAnalog Mixed-SignalTechnical Solution ManagementDesign SeminarsLow Power DesignBuck Converter DesignVery-Large-Scale Integration (VLSI)AnalogASICCircuit DesignApplication-Specific Integrated Circuits (ASIC)DebuggingCMOS

About

High-Speed SerDes • Ethernet • UALink • UEC • E-SUN • Scale-Up / Scale-Out / Scale-Across Fabrics • High-Performance Compute SoCs I help the world's leading silicon and hyperscale teams connect the next generation of AI and HPC systems. As Sr Director of Product Management at Synopsys, I lead a portfolio of high-speed interconnect IP that powers modern compute SoCs — including 56G / 112G / 224G / 448G SerDes PHYs, 400GbE / 800GbE / 1.6TbE Ethernet, Ultra Accelerator Link (UALink), Ultra Ethernet (UEC), E-SUN, and NVLink Fusion. My focus is turning emerging standards into production-ready silicon IP that scales up inside the rack, out across the data center, and across AI factories. Beyond Synopsys, I'm proud to serve as Secretary and Board Member of the UALink Consortium, helping shape the open standard for accelerator-to-accelerator connectivity. As an IEEE Senior Member, I also contribute to 224G and 448G specification development — working alongside the industry to define the interconnects that will carry tomorrow's AI workloads.

Experience

18 yrs 9 mos

Total Experience

3 yrs 3 mos

Average Tenure

10 mos

Current Experience

Ieee

Senior Member

Aug 2025 – Present · 10 mos

Ultra accelerator link consortium

Secretary Board of Directors

May 2025 – Present · 1 yr 1 mo

Ieee

IEEE 802.3 Working Group Voter

Mar 2021 – Apr 2025 · 4 yrs 1 mo

1.6TbE/800GbE Ethernet spec development with focus on linear electro optical interfaces

EthernetSpecification Development

Synopsys inc

Senior Director of Product Management

Sep 2018 – Present · 7 yrs 9 mos

Define, deploy, and manage High-Speed SerDes IP portfolio for next-generation protocols including PCIe, CXL, Ultra Accelerator Link, Ethernet, and Ultra Ethernet for advanced High Performance Computing System-on-Chips.

High-Speed SerDesEthernetHigh Performance ComputingSoC

Insilico

Director - Analog Mixed Signal Design

Sep 2017 – Sep 2018 · 1 yr · Bangalore

Started Analog Mixed Signal Design group at Insilico and grew the team in SerDes Design and Custom layout. Consulted a tier 1 ASIC company for 25.6 Gbps SerDes design in TSMC 16FFC.

Analog Mixed Signal DesignSerDes Design

Cadence design systems

Principal Engineer - High Speed SerDes IP Applications

Jul 2013 – Sep 2017 · 4 yrs 2 mos · San Jose

Technical Solution Manager responsible for the adoption of Cadence' Analog Mixed-Signal (ADC/DAC, PLLs), High Speed SerDes and Controllers (PCI Express, USB, MIPI and Ethernet) IPs in North America region
Influenced new product road-map and IP architecture with technology expertise in latest market trends in Automotive (Functional Safety, ISO26262, ASIL certification), enterprise networking/storage (CCIX, OpenCAPI, GenZ), deep learning (Tensilica processing unit, Interfaces) verticals
Represented Cadence at Industry’s leading tech forums: PCI-SIG, MIPI DevCon, Optical Fiber Conference, CDN Live, Design Automation Conference

Analog Mixed-SignalHigh Speed SerDesTechnical Solution Management

Analog devices

Systems Application Engineer

Jun 2011 – Jun 2013 · 2 yrs · Pune Area, India

Supervised technical support through independent design houses with on-site debugging of customer’s modules employing ADI devices
Conducted design seminars in the region to educate customers and develop eco-system

Technical SupportDesign Seminars

Applied micro circuits

Analog Design Engineer

Jan 2010 – May 2011 · 1 yr 4 mos · Pune Area, India

Designed an ultra-low power RTC SoC for processor applications in advanced TSMC technology to maximize RTC battery life. The SoC integrates a Band-gap voltage reference, a linear regulator and a comparator. US Patent granted for circuit innovation.
Designed high PSRR LDO for 10GHz PLL used in 10G-KR SerDes PHY in advanced TSMC process

Analog DesignLow Power Design

Cosmic circuits

Analog Design Engineer

Jul 2007 – Jan 2010 · 2 yrs 6 mos · Bengaluru Area, India

Developed expertise in on-chip voltage regulator architecture. Designed, characterized and verified a 3.6V-1.2 V current mode compensated Buck converter with 0.47uH inductor and 4.7uF capacitor off-chip for 800 mA load current in TSMC 40 process – silicon proven
Implemented PFM (Pulse Frequency Modulation) switching scheme in a Buck converter to achieve high efficiency (85%+) at low loads (1mA-)
Designed and characterized On-Chip Current Sensing IP to measure current with 1% accuracy over load current range from 1mA to 800mA of a Buck converter

Voltage Regulator DesignBuck Converter Design