Ani Muradyan

Software Engineer

Ireland15 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in timing methodology development for advanced technologies.
Proficient in physical design and verification across multiple nodes.
Strong background in quality assurance and automation testing.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in timing and quality assurance.

Contact

Skills

Core Skills

Timing MethodologyIntegrated Circuits (ic)Quality AssurancePostman ApiPhysical Design

Other Skills

Timing package generationTiming methodology developmentCorner page/mapping generationProcess evaluationWebstormData Collection Application testingFunctional and End-to-end Flows automationJavaScript automation testsSelenium WebDriverJira ticket creationFloorplanningPlace & RoutePhysical verificationRCXCMOS

Experience

15 yrs 7 mos

Total Experience

4 yrs 7 mos

Average Tenure

1 yr 10 mos

Current Experience

Qualcomm

Senior Timing Engineer

Aug 2024 – Present · 1 yr 10 mos · Cork, County Cork, Ireland · Hybrid

Corner page/mapping generation for 6nm, 3nm, 2nm technologies
Process evaluation of 4nm, 3nm, 2nm technologies
Timing package generation/validation,
Timing methodology development.

Timing package generationTiming methodology developmentCorner page/mapping generationProcess evaluationTiming methodologyIntegrated Circuits (IC)

Synopsys inc

6 roles

Staff Quality Assurance Engineer

Feb 2024 – Aug 2024 · 6 mos

Advantest, FT-PAT ACS Edge Application, Data Collection Application manual test and automation of Functional and End-to-end Flows.
ML Vmin, Parametric Prediction results manual testing on Cloud Front End platforms, parallel to Kubeflow Pipelines.

Postman APIWebstormData Collection Application testingFunctional and End-to-end Flows automationQuality Assurance

Senior I Quality Assurance Engineer (Staff)

Jan 2023 – Aug 2024 · 1 yr 7 mos

Advantest, FT-PAT ACS Edge Application, Data Collection Application manual test and automation of Functional and End-to-end Flows.
ML Vmin, Parametric Prediction results manual testing on Cloud Front End platforms, parallel to Kubeflow Pipelines.
Development of JavaScript automation tests based on Selenium WebDriver for Regression processes.
Creation Jira tickets.

WebstormJavaScript automation testsSelenium WebDriverJira ticket creationQuality Assurance

Senior I ASIC Physical Design Engineer (Staff)

Promoted

Dec 2020 – Dec 2022 · 2 yrs

- The standard cells place & route for 28nm, 20nm, 16nm, 14nm 7nm 5nm technologies using ICC ICC2 Compiler.

FloorplanningPlace & RouteIntegrated Circuits (IC)Physical Design

ASIC Physical Design Engineer II (Senior)

Promoted

Jun 2018 – Nov 2020 · 2 yrs 5 mos

Advanced knowledge of Floorplan, Power routing, placement, Zroute.
Experience with physical verification of routed blocks (DRC, LVS).
The standard cells place & route for 28nm, 20nm, 16nm, 14nm technologies using ICC Compiler.

FloorplanningPlace & RouteIntegrated Circuits (IC)Physical verificationPhysical Design