Ponrajkumar Pandiyan

Software Engineer

Tamil Nadu, India6 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in C++ and Object-Oriented Programming.
Significant contributions to semiconductor design tools.
Strong background in pattern porting and debugging.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in design tools and pattern porting.

Contact

Skills

Core Skills

C++Object-oriented Programming (oop)LinuxDebuggingVerilogProblem SolvingTeaching

Other Skills

Shell ScriptingRegression TestingDesign PatternsData StructuresCodingCommunicationTrainingBack-End Developer

About

As a Staff R&D Engineer at Synopsys, a premier provider of software solutions for integrated chip design and validation, I play a pivotal role in the development and enhancement of critical features for Synopsys TestMax Manager. This tool expedites and refines the testing process of chips, and is complemented by my contributions to pattern_shell, StilGen, and stil2pdl tools. My collaborations span across teams in three different geographies, ensuring a global impact of our collective efforts. My academic background includes a M.Tech. in Computer Science and Data Processing from IIT Kharagpur, completed in 2021. This has provided a solid foundation for my professional expertise in C/C++, object-oriented programming, and design patterns. I have a particular interest in code optimizations and the design of reusable object-oriented software. I am also committed to continuous learning and staying updated with new skills and technologies in the field.

Experience

6 yrs 8 mos

Total Experience

3 yrs 4 mos

Average Tenure

5 yrs

Current Experience

Synopsys inc

2 roles

R&D Engineering Staff

Dec 2023 – Present · 2 yrs 6 mos

Hierarchical DFT Flow Development:
Working on development of a pattern porting tool, which port core level patterns to the top level.
Actively involved in the creation and enhancement of STIL and SPF editing tools, contributing to the efficiency and accuracy of the design process.
Working on development of pattern porting for 2.5DIC, ensuring compatibility and functionality across different integrated circuit designs.
Unified Shell Development:
Actively involved in linking various tools to create a unified platform that can execute commands from all integrated tools.
Working on the transfer of data between tool databases internally to enhance the user experience through seamless data accessibility and interaction.
STIL to PDL Converter Software Enhancement:
Actively contributing to the enhancement of the STIL to PDL converter software, specifically for generating the STIL for XLBIST.

Problem SolvingDebuggingC++Object-Oriented Programming (OOP)

R&D Engineer II

Jun 2021 – Dec 2023 · 2 yrs 6 mos

Streaming Fabric Pattern Porting:
Enabled core to top pattern porting through Streaming Fabric.
Provided support for pattern porting in multibranch and hybrid configurations.
Contributed to the generation of SpyGlass Design Constraints (SGDC) to verify connections within the streaming fabric.
3DIC Pattern Porting:
Played a key role in enabling pattern porting from the die level to stack level in 3DIC designs.
STIL to PDL Converter Software Enhancement:
Led the enhancement of the existing STIL to PDL tool for IEEE 1687 (IJTAG) standard.

Problem SolvingDebuggingC++Object-Oriented Programming (OOP)