Saptak Acharjee

Software Engineer

Kolkata, West Bengal, India6 yrs 10 mos experience

AI EnabledHighly Stable

Key Highlights

Expert in VLSI and microelectronics with advanced physical design skills.
Proven track record of delivering PPA improvements under tight schedules.
Strong programming skills in Python, C, and C++ for machine learning applications.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in VLSI and machine learning applications.

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Skills

Core Skills

Physical DesignVlsi

Other Skills

PNRFC compilerPPA improvementFusion CompilerCTS flow debuggingSTASynthesisFloorplanPower planRTL2GDS flow stabilizationRC correctionCompile optClock Tree SynthesisClock optGlobal routing

About

As a R&D Physical Design, Staff Engineer at Synopsys, I work with leading semiconductor companies to provide them with innovative and optimized solutions for their physical design challenges. I use my expertise in Synopsys tools and cutting edge technology solution to enable faster and more reliable design closure and verification. I have a strong background in VLSI and microelectronics, which I developed during my Master of Technology degree at the Indian Institute of Technology, Madras. I also have proficiency in Python, C, and C++, which I apply to implement machine learning algorithms for improving the efficiency and accuracy of physical design processes. I am passionate about learning new technologies and solving complex problems in the field of electronic design automation.

Experience

6 yrs 10 mos

Total Experience

2 yrs 10 mos

Average Tenure

1 yr 1 mo

Current Experience

Samsung semiconductor

SOC Physical Design, Staff Engineer

May 2025 – Present · 1 yr 1 mo · Bangalore · Hybrid

Synopsys inc

2 roles

ASIC Physical Design, Staff Engineer

Jan 2025 – May 2025 · 4 mos · Hybrid

R&D Physical Design, Sr. Engineer

Dec 2022 – Dec 2024 · 2 yrs · Hybrid

Intel 18A Tech node:
Executed PPA push for Fusion Compiler T build version and delivered 4% PPA improvement to Intel with tight project schedule
Owner of a Multi-clock test block with both functional and test Pvt corners and Back power metal layers
Gained expertise in Frequency push and power reduction techniques as well as flow debugging techniques
Provided enhancement for better Virtual route (compile) vs Global route (clock opt) and Global Route (clock opt) vs Detailed route (route opt) correlation which leads to the better PPA
Worked on Synopsys new flow features for complex node design convergence like Trackopt, Wireopt, Early GR, restrict VT etc
Intel 14A node:
Worked few months on Intel 14A project to debug and provide solution for CTS flow bug fixes regarding multi-clock sources

PNRFC compilerPhysical DesignVLSI

Intel corporation

CPU Physical Design Engineer

Jul 2019 – Dec 2022 · 3 yrs 5 mos · India

Intel 7nm Tech node:
Owned Highly complex large multi-clock and multi-power Block of ~1M instances with multiple functional and test pvt corners
Executed Synthesis, Floorplan, IO placing, power plan, PNR, ECO, STA, PV, EMIR, Noise fixes, FEV
Handled complex UPF of the MV design strategies and complex SDC’s of clock congested multi-clock domain block
As a power management block in the full chip with multiple clock domains, required to take care of many CDC synchronous and asynchronous clock paths with MCP, False path, zero cycle setup paths etc
Cleaned up big logic cones in formality which was due to the logical complexity of different clock syncs and power domains
Achieved tight power targets by using different power reduction recipes
Intel 20A Test chip:
Own and Stabilise Cheetah-II RTL2GDS flow for different blocks in this Testchip
Lead a Team of 5 members working on this Test chip project
Performed complete Ownership of a block which was dominated by Macros with different voltage domains and Intel’s new Back metal layer technology