Sep 2025 – Present · 9 mos · Bengaluru

• Verified vendor provided ARAGIO GPIO IP in ADICE by evaluating transmitter/receiver functionality across multiple drive strengths, slew rates, supply voltages and operating frequencies. Built a Simultaneous Switching Output(SSO) analysis setup by instantiating IO pads and modeling capacitive coupling, inductive coupling, power parasitics, package parasitics and transmission line effects for various load capacitances. Analysed VDD bounce and Ground bounce and incorporated termination.
• Worked on a 1.2 V op amp based BGR incorporating a startup circuit with BJT ratios of 1:8. Achieved a 1.2 mV deviation at the typical corner and ±7 mV deviation across PVT. For this, designed a two-stage PMOS input pair op-amp suitable for BGR operation across PVT with a gain greater than 65 dB. Incorporated Miller compensation for stability. Also worked on a 0.5 V low voltage BGR for the typical corner.
• Worked on glitch free clock divider f/2, f/4 and f/8. Achieved PSIJ of 1.8ps and Random Jitter of 260fs. Average Power consumed is 70uW.
• Working on CML to CMOS converter.