Gaurav Gupta

Director of Engineering

India14 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in memory design and testing.
Proficient in low power design techniques.
Strong background in EDA and circuit verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in EDA tools and low power systems.

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Skills

Core Skills

Circuit DesignVerificationSimulationLow Power Design

Other Skills

Bit Cell AnalysisRead/Write margin analysisTiming/Bist margin analysisFlip time analysisPower & Leakage correlationTrend mismatch AnalysisTiming CharacterizationComplier IntegrationAMS-CPF simulationRTL descriptionDRC/LVSRCXCadence PVSAssuraCPF enabled low-power support

About

Currently working as an Engineering Manager handling various activities related to memory design and testing Previously, have worked in the EDA domain helping proliferate tool solutions at the customer end

Experience

14 yrs 6 mos

Total Experience

7 yrs 3 mos

Average Tenure

11 yrs 9 mos

Current Experience

Synopsys inc

5 roles

Senior R&D Manager

Promoted

May 2026 – Present · 1 mo

R&D Manager

Dec 2021 – Present · 4 yrs 6 mos

Sr R&D Engineer II

Jul 2019 – Dec 2021 · 2 yrs 5 mos

Sr. R&D Engineer

Nov 2016 – Jun 2019 · 2 yrs 7 mos

R&D Engineer

Aug 2014 – Nov 2016 · 2 yrs 3 mos

Involved in Circuit Design & Verification of Pseudo-Dual Port UHD variant of SRAM at 10nm.
Work profile includes:
Bit Cell Analysis
Read/Write margin analysis
Timing/Bist margin analysis
Flip time analysis
Power & Leakage correlation
Trend mismatch Analysis
Timing Characterization
Complier Integration

Circuit DesignVerificationBit Cell AnalysisRead/Write margin analysisTiming/Bist margin analysisFlip time analysis+4

Cadence design systems

3 roles

Member of Technical Staff

Jul 2014 – Jul 2014 · 0 mo

Responsible for the verfication of the complete flow, which involves AMS-CPF simulation(after formal verification) from the RTL description and then DRC/LVS and RCX through Cadence PVS/Assura.
The same is carried out with customers'/in-house IPs.

AMS-CPF simulationRTL descriptionDRC/LVSRCXCadence PVSAssura+2

Product Support Engineer

May 2012 – Jun 2014 · 2 yrs 1 mo

Worked on the implementation of CPF enabled,low-power support in the Cadence Virtuoso.
Responsibility involves :
Engaging with customers to debug their IPs,exploiting various low power techniques such as Multi-Supply Voltage; Power-Shutoff etc. for macro-level and design level use and thus help them to reduce/automate the design cycle by enabling them to use the designated solution for macro/design level CPF generation.
Verification of the CPF file generated by Virtuoso and carry out the formal verification for the same, through Encounter Confromal Low Power.

CPF enabled low-power supportDebuggingLow power techniquesFormal verificationLow Power DesignVerification