Akshata Kori

Product Manager

Bengaluru, Karnataka, India9 yrs 8 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Expert in UVM-based verification for VLSI design.
Hands-on experience in AI and machine learning deployment.
Strong background in physical design and timing analysis.

Stackforce AI infers this person is a VLSI and AI specialist with expertise in design verification and physical design.

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Skills

Core Skills

Uvm-based VerificationAi And Machine LearningPhysical DesignStatic Timing Analysis

Other Skills

TCLSTAUVMAMBA-3 APB 2.0AIMachine LearningPyTorchHugging FaceFunctional coverageSynopsys ICC2_ShellPerlTiming AnalysisMATLABC (Programming Language)SystemVerilog

About

I’m an Assistant Professor at Ramaiah Institute of Technology, passionate about bridging VLSI design, verification, and AI innovation. I specialize in UVM-based verification for AMBA-3 APB 2.0, building robust environments with drivers, monitors, and scoreboards using UVM constraints and randomization. With hands-on expertise in digital physical design (Synopsys ICC2_Shell) and Perl/Tcl scripting, I explore low-power techniques like clock gating and multi-voltage design. My interest in AI and ML—using PyTorch and Hugging Face—drives my work in LLM deployment and intelligent systems research. I’m driven by curiosity, collaboration, and the goal of turning cutting-edge ideas into real-world impact across VLSI and emerging technologies.

Experience

9 yrs 8 mos

Total Experience

4 yrs 10 mos

Average Tenure

7 yrs 9 mos

Current Experience

Rv-vlsi vlsi and embedded systems design center

Physical Design Trainee

Aug 2022 – Feb 2023 · 6 mos · Bengaluru, Karnataka, India · On-site

Hands-on experience in Physical Design using Synopsys ICC2_Shell in the 40nm technological node with efficient area, power, and timing optimization.
Hands-on experience in STA using Synopsys Prime Time for timing analysis and finding violating timing paths.
Knowledge of scripting languages such as Shell, Perl, and Tcl.
Manual placement of macros by analyzing IR drop and routing congestion based on data flow lines, macro family, and ports for creating floorplan.
Placement of cells by optimizing the timing, power, area, routability, congestion, and timing.
Building up the clock tree by meeting the skew.
Route all nets in design with wire length and routability optimized.
For interpreting timing reports in STA and fixing violations by calculating various parameters such as Setup Slack, Hold Slack, and Propagation delay.
Interpreted and fixed DRC and LVS errors during floorplan, placement, CTS, and Routing stages of Physical Design.

Synopsys ICC2_ShellSTAPerlTCLTiming AnalysisPhysical Design+1

Ramaiah institute of technology

Assistant Professor

Sep 2018 – Present · 7 yrs 9 mos · Bengaluru · On-site

5+ years of experience in academia in the Dept. of Electronics and Telecommunication at Ramaiah Institute of Technology, Bangalore.
Experienced in developing UVM-based verification environments for AMBA-3 APB 2.0 protocols, including driver, monitor, and scoreboard creation.
Skilled in applying assertions, functional coverage, and UVM methodologies such as constraints, randomization, and OOP principles.
Knowledge of the digital PD Flow RTL to GDS
Understanding of low-power techniques including clock gating, power gating, and multi-voltage designs.
Expertise in AI and machine learning platforms, including PyTorch and Hugging Face, with hands-on experience in deploying Large Language Models (LLMs) using LangChain.
Excellent problem-solving, leadership, and collaborative skills

TCLSTAUVMAMBA-3 APB 2.0AIMachine Learning+4

Crucible of research and innovation, pes

Research Assistant

Sep 2016 – Aug 2018 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Provide research support for PI-SAT development.
Research and analysis of space grade components for PI-SAT.
Study on Orbit Dynamics and Kinematics
Develop and write research reports.
Study projects, designing and programming for improvising the solution of the problem statement of the project

MATLABC (Programming Language)