Ravinder Chahal

CEO

Bengaluru, Karnataka, India14 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in CXL and PCIe verification methodologies.
Proven track record in leading verification projects.
Strong background in functional coverage and compliance testing.

Stackforce AI infers this person is a Verification Engineer specializing in EDA tools and methodologies.

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Skills

Core Skills

CxlFunctional CoverageDebuggingCompliance TestingPcieRelease ManagementInterlakenFunctional VerificationRegression Testing

Other Skills

TestplanregressionCXSCCIXCustomer SupportValidationRegression AnalysisProduct DevelopmentEnumerationVerilogSystemVerilogCVLSISoCSystem on a Chip (SoC)

About

An accomplished, motivated, result oriented professional with experience in Verification IP & emulation. Having strong skills in Verification methodologies like UVM & OVM, System Verilog & Verilog, C, C++, scripting. Exposure to EDA industry standard tools like VCS, Questa, Xcelium, Verdi, ZEBU etc. tool and verification traceability via Functional coverage & test plans with Verification planner. Knowledge of wide industry used protocol like CXL(Compute Express Link), PCIe, NVMe, CCIX, AMBA (APB,AHB,AXI,ACE,CHI), I2C, I3C, SDIO, UART, ONFI, JESD204B etc.

Experience

14 yrs 7 mos

Total Experience

10 yrs 11 mos

Average Tenure

3 yrs 8 mos

Current Experience

Marvell technology

2 roles

Senior Staff Manager

Promoted

Sep 2025 – Present · 9 mos

Principal Engineer

Oct 2022 – May 2026 · 3 yrs 7 mos

Synopsys inc

4 roles

Research and Development Staff

Dec 2020 – Oct 2022 · 1 yr 10 mos

Verification & Development of CXL Verification IP & Test Suite | Compliance testing | Enumeration | RAS | Security | Functional Coverage | Testplans | Verification Planner | Debugging | Synopsys CXL Controller | Synopsys Cryptography Library | DOE | CMA | SPDM | AES-GCM | Verdi | VCS (2-Step/3-Step) | Testbench Architecture
Security Verification IP: AES-GCM based encryption & decryption for usage in CXL & PCIe Product.
PCIe Accelerated VIP: Customer support, XTOR integration, ZEBU validation.

Functional CoverageCompliance TestingCXLDebuggingTestplan

Senior Research And Development Engineer

Promoted

Jul 2016 – Nov 2020 · 4 yrs 4 mos

Synopsys PCIe Controller | PCIe Transaction Layer | Transaction Layer packets | Ordering | CCIX | CXS | Multi-layer VIP development | Customer support | Testplans | Functional coverage | Emulation | HW-SW Co-verification | ZEBU | VCS | Questa | IUS | Verdi | DVE
PCIe Application Layer VIP : Development (Credits management, CXS & CCIX support, sideband interfaces support, ordering support etc.), integration with controller, verification, customer support, regression, release, managing team.
PCIe Accelerated VIP (AVIP) : Development of DPI-C Layer for PCIe VIP & XTOR integration, performance analysis, PCIe TestSuite integration, customer support, verification, regressions, release.
Interlaken: RS-FEC feature integration, customer support for RS-FEC.
CCIX : Integration with PCIe VIP, CXS support for CCIX.

PCIeregressionCXSCCIXInterlakenRelease Management

R & D Engg. II

Promoted

Jun 2014 – Jun 2016 · 2 yrs

Verification IPs : AMBA ACE, PCIe, NVMe, CHI,AXI, I2C, I3C, UART, JESD204B, ONFI, MIPI
JESD204B: Receiver development
ONFI1.0: Master development
AMBA ACE/CHI: Accelerated VIP Testbench development
MIPI DBI: Transmitter development
AXI,I2C,I3C,UART: Feature/Testbench developments
PCIe/NVME : Specification understanding

R & D Engineer I

Sep 2011 – Jun 2014 · 2 yrs 9 mos

Verification IP : AMBA AHB, AXI, SD,SDIO
OVM | UVM | OVM2UVM | OVM Based Test & Sequence Development | Scoreboard development | Regression Testing & Analysis | Functional coverage | Protocol checkers | Debugging | Release management | Customer support

ValidationRegression TestingFunctional VerificationRegression AnalysisProduct Development