Jeetesh Chaturvedi — Software Engineer

☛ Always eager to learn state of the art technologies & moving forward by updating myself with the advancements in Science & Technology. Working as an AMS Cricuit Design Engr, my role is to work with DDR PHY designs which includes calibration block, RX, TX & other modules. I have also worked as a Corporate Application Engineer, where my role was to work on partitioning the complex SoC designs over multiple FPGA Synopsys HAPS board systems. I have good understanding & working experience on synthesis of designs on Xilinx Virtex Ultrascale & Virtex-7 FPGA. Automation of FPGA flow & debugging using Tcl scripting in Unix environment. I am working with following tool sets: ● Circuit Design Tool-set: Custom Designer-HSPICE/FineSim ● Partitioning: Protocompiler, Certify ● FPGA Synthesis: Synopsys Synplify Pro & Synplify Premier ● Placement & Routing: Xilinx Vivado ● Debugging: Verdi ☛ Completed my Post-Graduation in VLSI Design from ABV - Indian Institute of Information Technology & Management Gwalior, with a high propensity towards learning and having the aim of directing this energy into creating an advanced VLSI Design technology with pervasive contribution.

Stackforce AI infers this person is a VLSI and FPGA design specialist with a focus on ASIC prototyping.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 1 mo