Mar 2017 – Jun 2019 · 2 yrs 3 mos · Bengaluru Area, India

• Cadence SoC Design Services Group
• Responsible for all backend activities (Netlist to GDS) for customers in IOT, smart-watches, CPU & Networking chip design in 65nm/55nm/28nm/16nm technology nodes with TSMC and SMIC Foundries.
• 5 successful tapeout's, crafting customers success and making few of them come back again.
• Created solution plan on complex clocking circuits for Networking chips in MMMC to address postCTS hold violations with skew balancing and solving the cross corner delay scaling issues.
• Handled upto ~5 Million instance design and created creative solutions to reduce congestion/DRC, resolving timing violations & reduced the overall leakage power at the backend.
• Strong knowledge in PnR Methodology and deep understanding in Cadence EDA tools, addressed issues like pre to post routing & innovus to tempus correlation problems.
• Received 4 times directors award for excellence in Quality Delivery and Flawless Execution.
• Received special recognition from Customers by beating legacy QoR results and helping them to improve products while pushing for QoR.

Dec 2015 – Mar 2017 · 1 yr 3 mos

• SoC Design Solutions, ICF Group.
• Performed backend Netlist-to-GDS, physical verification and timing closure activities at block and FC level. Contributed to 7 successful tapeouts for 2 products & 5 test chips across Intel’s 32nm, 22nm 14nm & 10nm technology nodes.
• Good knowledge and exposure to physical design domains mainly in floor-planning, placement, clock tree synthesis, routing, ECO implementation STA fixes, physical verification DRC/LVS fixes, IR drop analysis, XOR and LEC checks.
• Demonstrated running extra miles to collaborate & work with external tool vendors mainly from Cadence and Synopsys to improve QOR and performance of ASIC flow. Have good experience working along with the internal DA team to identify, analyze and provide fixes for all issues caught in ASIC flow to improve ASIC Design Methodology.

Sep 2013 – Dec 2015 · 2 yrs 3 mos

• Responsibilities mainly included activities at Backend Implementation from Netlist – Tapeout.
• Well versed to understand and perform ASIC integration checks for internal and external IP’s, worked along with RTL architects to meet best QOR results for IP specific ASIC design at backend stage.
• Good exposure towards fixing IR drop, RV and metal/via and base layer fill mostly with correct by construction method.
• Have demonstrated excellent communication, presentation and coordination skills for training and leading external teams for multiple projects, planning achievable milestones. Showed passion for providing skillset training to newly joined graduate engineers in the team.

Jan 2010 – Jul 2010 · 6 mos · Bangalore, India

• Full custom IC design implementation from Spec to Package integration for RF Driver unit, Weather Doppler RADAR systems.
• Team lead for the project mentoring six other interns, and acquired project management skills.