Anish Mon — Project Manager

Comprehensive understanding of the ASIC design flow from RTL to GDSII and its implementation processes Hands-on experience in implementing APR flow including Floorplan, Powerplan, Placement, CTS and Routing Interpreted and fixed Design Violations such as Congestion, Overlaps, IR drop, EM, Crosstalk & Timing violations Designed and optimized a Block Level Design using low power design techniques to improve Power, Performance & Area while meeting the PVT constrains Performed Physical Verification checks and cleared DRC, LVS, ERC and Antenna issues to ensure design integrity Excellent command in STA, generated and interpreted timing reports for false paths, half and multi cycle paths Understanding of Synthesis and IC Fabrication Process and its various stages and techniques Knowledge of Analog Layout concepts such as Matching, Electro-migration, Latch-up, Antenna effect, Cross-talk, IR-drop, WPE and STI. Understanding of layout parasitics and their impact on the performance and reliability of a design. Familiar with IC fabrication process and its various stages and techniques. Comprehensive insight on FinFET layout principles and intricacies. High learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

Stackforce AI infers this person is a Physical Design Engineer with expertise in ASIC and VLSI technologies.

Location: Bengaluru, Karnataka, India

Experience: 6 mos