Mohit Saini — Software Engineer

I am an experienced RTL Design Engineer with a strong foundation in processor microarchitecture, hardware accelerators, and RTL development. I’ve worked across industry-leading organizations like Microsoft and Qualcomm, delivering complex, production-grade silicon designs optimized for performance, power, and scalability. At Microsoft, I’m currently driving RTL architecture and implementation for next-generation server hardware powering Azure. My work focuses on building custom hardware accelerators for: • Data compression and decompression (LZ77, Huffman, ZIP, Zstandard) • An NFA-based Regex engine for high-speed pattern matching • A completion queue generator for RDMA, enabling low-latency, scalable networking in cloud datacenters This involves designing high-throughput, power-efficient datapaths and control logic tailored for hyperscale infrastructure. Previously at Qualcomm, I led RTL development and microarchitecture design across multiple processor platforms. My work spanned instruction fetch, multi-threading, memory management, security, QoS, L1/L2 caches, and AMBA AHB/AXI-based interconnects. I delivered end-to-end RTL designs that met aggressive performance and power goals across advanced tech nodes. Across both roles, I have: • Defined microarchitectures from scratch • Owned SystemVerilog RTL implementation • Led DFT, CDC, Lint, and Fishtail closure • Driven formal/functional verification • Handled emulation and silicon debug • Used Git-based flows and industry-standard EDA tools . In summary, I bring a proven ability to design and deliver scalable, efficient, and silicon-proven RTL for processors and accelerators—tailored for modern compute and networking workloads. My goal is to continue building future-ready hardware that powers the cloud and beyond.

Stackforce AI infers this person is a Cloud Computing and Hardware Engineering expert focused on scalable processor design.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 7 mos