Vengal reddy

DevOps Engineer

Hyderabad, Telangana, India9 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC Digital Design and System-on-Chip engineering.
  • Proficient in multiple programming languages and design methodologies.
  • Strong background in logic synthesis and static timing analysis.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.

Contact

LinkedIn

Skills

Other Skills

CTCLPerlVerilogC++UnixLECCDCLogic SynthesisStatic Timing Analysis

Experience

9 yrs 1 mo
Total Experience
2 yrs 3 mos
Average Tenure
3 yrs 4 mos
Current Experience

Synopsys inc

3 roles

ASIC Digital design, Sr Staff engineer

Promoted

May 2026 – Present · 1 mo · On-site

ASIC Digital Design Staff Engineer

Promoted

Feb 2024 – May 2026 · 2 yrs 3 mos · On-site

ASIC Digital design Engineer Sr I

Feb 2023 – Feb 2024 · 1 yr · On-site

Intel corporation

System-on-Chip Design Engineer

Aug 2020 – Feb 2023 · 2 yrs 6 mos · Bengaluru South, Karnataka, India

  • great place to work.. i really enjoyed working in intel

Soctronics

2 roles

Design Engineer 2

Promoted

Nov 2018 – Aug 2020 · 1 yr 9 mos

Design Engineer 1

Nov 2017 – Nov 2018 · 1 yr

Vedaiit

LD

May 2017 – Nov 2017 · 6 mos

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Microelectronics

Jun 2023 – May 2025

Annamacharya Institute of Technology & Sciences,(Autonomous) New Bowenpally, Rajampet

B.tech — Eletronics & Communication

Jan 2013 – Jan 2017

sri gayatri jr college, tirupati

MPC

Jan 2011 – Jan 2013

Jawahar navodaya vidyalaya kadapa

Schooling — VI- X th

Jan 2006 – Jan 2011

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