Phu Tran

Software Engineer

Da Nang City, Vietnam6 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in Analog & Mixed Signal Design.
  • Proven leadership in semiconductor projects.
  • Strong background in training and development.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed Signal Design.

Contact

LinkedIn

Skills

Core Skills

Analog Circuit DesignCmosPhysical Design

Other Skills

HspiceTCLCshellStatic Timing AnalysisPerlTiming CharacterizationCircuit DesignDigital Circuit DesignCustom CompilerSynopsys IC CompilerFinesimVerilog-AEMIRProject PlanningTeam Leadership

About

"Nothing or All In." Perfectionist, extroverted introvert, enthusiastic, courteous and opened mindset. I am currently working in Analog & Mixed Signal Design field. My goal is to gain as much skills and experiences in this semiconductor industry as possible in the upcoming years. Advancing to a Leader position or taking a further step oversea for a Master degree, and finally end up as a Design Manager, or a Technical Manager, involving in Recruitment & Training before the age of 35.

Experience

6 yrs 7 mos
Total Experience
2 yrs 10 mos
Average Tenure
10 mos
Current Experience

Mixel vietnam

AMS Circuit Design, Staff Engineer

Aug 2025 – Present · 10 mos

Synopsys inc

3 roles

A&MS Circuit Design, Senior Engineer

Promoted

Feb 2024 – Aug 2025 · 1 yr 6 mos · Da Nang City, Vietnam

  • UCIE 4nm 16Gbps - Clocktree Design Lead
  • UCIE2 3nm 32Gbps - IOTX Circuit Design
  • UCIE3 2nm 64Gbps - Clocktree & Phase Generator Circuit Design
  • Internship Trainer - Basic CMOS Theory & Simulation
Analog Circuit DesignCMOS

A&MS Circuit Design, Engineer II

Promoted

Feb 2023 – Aug 2025 · 2 yrs 6 mos · Da Nang City, Vietnam

  • UCIE 3nm/5nm 16Gbps/20Gbps - Clocktree/DCA/LCDL - Design Lead
CMOSHspice

A&MS Circuit Design, Engineer I

Jun 2022 – Feb 2023 · 8 mos · Da Nang City, Vietnam

  • UCIE 5nm - DCA (Duty Cycle Adjustment) - IP Owner

Savarti ltd.

3 roles

A&MS Circuit Design Engineer

Promoted

Sep 2020 – Jun 2022 · 1 yr 9 mos

  • Standard Cells Liberty Characterization, PLL, LPDDR5-IO
  • 7nm, 16nm
TCLAnalog Circuit Design

Physical Design Engineer

Apr 2020 – Sep 2020 · 5 mos

  • RTL2GDS - 28nm
Physical Design

Intern

Oct 2019 – Mar 2020 · 5 mos

  • Single Port SRAM 1024x32 - 28nm
TCLCshell

Education

Danang University of Science and Technology

Engineer's degree — Electronic and Telecommunication Engineering

Jan 2015 – Jan 2020

Le Quy Don High School for the Gifted-Danang

Mathematics

Stackforce found 100+ more professionals with Analog Circuit Design & Cmos

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