Pankaj Baghmar

Software Engineer

Germany10 yrs 5 mos experience

Highly Stable

Key Highlights

9+ years in semiconductor physical design.
Expert in IC backend implementation from synthesis to GDS.
Proficient in managing teams and training new engineers.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with extensive experience in backend design and team management.

Contact

Skills

Core Skills

Ic Physical DesignPlace & RoutePhysical Design

Other Skills

Synthesis to GDSEM/IR analysisLow power designShell scriptingPerl scriptingTcl scriptingSTA closurePNRSign-offEM/IRBump planningTiming ClosureLogical and Physical VerificationEngineering

About

I am a Physical Design Engineer with 9+ years of experience in the semiconductor industry, working as a Sr Staff Engineer at Infineon Technology , Munich , Germany.Currently I design IC chips for Automotive industry. My expertise lies in the Physical Design backend implementation of IC SOC/ASIC from Synthesis to GDS, covering various domains, such as mobile, network, graphics, wifi, optical, storage, Automative and sensor chips. I have delivered high-quality and high-performance products for AMD, Mediatek, ARM, and Maxlinear, by successfully closing multiple top and block level designs. I have strong skills in PNR, sign-off, STA, EM/IR, low power design, parasitic extraction, and logical and physical verification, using various tools from Synopsys, Cadence, and Ansys. I am also proficient in scripting languages, such as shell, Perl, and Tcl, and have experience in managing and training teams, building flows and methodologies, and solving complex design challenges. I was responsible for EM/IR closure for 5nm full chip complex Design My goal is to leverage my expertise and passion for Physical Design to create innovative and impactful solutions for the semiconductor industry, and to continuously learn and grow as a professional.

Experience

10 yrs 5 mos

Total Experience

4 yrs 1 mo

Average Tenure

2 yrs 3 mos

Current Experience

Infineon technologies

Senior Staff Engineer IC Physical Design

Mar 2024 – Present · 2 yrs 3 mos · Munich, Bavaria, Germany · On-site

IC Physical DesignPlace & Route

Maxlinear

Staff Engineer -IC Physical Design

Nov 2019 – Dec 2023 · 4 yrs 1 mo · Spain · On-site

I am responsible for Top and block level Physical design backend implementation.I was also managing and training others. I have experience in PNR (Place and route), Signoff (LVS,ERC,DRC,EM,IR,Antenna etc) Floorplan, placement,cts,route, extraction . I have experience in various tool of synopsys ,cadence and Ansys.I was responsible for EM/IR analysis of 5nm complex full chip.
Primary Skills : Synthesis to GDS
PNR , Worked in TOP and Block level. Parasitic Extraction, Running EM/IR ,Post Layout timing closure and Sign off (LVS,DRC,ERC,IR,Antenna ,etc)
Scripting: Good knowledge of shell , Perl , Tcl scripting
Timing: Strong background in STA closure
Technologies Node: 5nm,7nm, 16nm,14nm, 55nm
Foundry: TSMC , samsung, UMC
Managing team
Training new Team members
Low power design
Tools:
Synopsys:ICC2,Primetime,FC,StarRC,ICV
Candence:Innovus, and Tempus ,QRC
Caliber from Mentor graphics
Redhawk & RH-SC from Ansy
Project1 (Data center): Responsible for PNR & sign-off of Top-level, Bump planning, ALRDL routing, manual power plan, Handling EM/ IR for entire project, helping in flow ,sign off and lot more. 5nm TSMC.
Project2 (Storage accelerator & Powerful data reduction technology): Responsible for PNR and sign-off for 4 blocks ,One block had 9M instance. Bump planning of top level ,manual power plan for effuse ,top layer ALRDL routing and pin placement ,flow fix and lot more. TSMC16. I was also handling full sub system. Managed & trained others
Project3 (Broadband): Responsible for Multiple block PNR and sign off and help in Top level and flow fix . UMC14 nm Technology
Project4 (Wifi) : TSMC16nm.Responsible for running multiple block PNR .
Project5 (Wifi) :Samsing 14nm.Responsible for running multiple block PNR.
Project6 : I was involved in few more project , flow development, training others , managing, recruitment activities and many more.

Place & RoutePhysical DesignSynthesis to GDSEM/IR analysisLow power designShell scripting+3

Synapse design inc.

Sr Engineer IC Physical Design -VLSI

Jul 2015 – Aug 2019 · 4 yrs 1 mo · Bengaluru, Karnataka, India · On-site

I worked here for more than 4 year. I was responsible for block level PNR(Place and route) and sign off (STA,ERC,DRC,Antenna,LEC etc). I worked in multiple tape outs for AMD,Mediatek,ARM.
Project 7 (Mediatek Ethernet): Responsible for Complete PnR, Timing Closure , Logical and Physical Verification & sign off .Frequency 1GHZ , 3M instance , 424 srams ,7nm Technology .PNR in ICC2.Low power design.
Project 8 (Mediatek Mobile SOC): Responsible for Complete PnR, Timing Closure , Logical and Physical Verification & sign off .Frequency 0.54 GHZ , 2.6M instance , 80 srams , 7nm Technology. PNR in INNOVUS . Low power Design.
Project9 (AMD Graphics processor):Responsible for Complete PnR, Timing Closure , Logical and Physical Verification & sign off for multiple block . Sram dominated design .7nm Technology ,PNR in ICC2 .High Operating frequency of 1.66Ghz. Low power design.
Project10 (ARM graphics processor): Responsible for Complete PnR, Timing Closure & sign off. Frequency - 500Mhz Tool Used : ICC2
Primary Skills : Synthesis to GDS
PNR , Worked in TOP and Block level. Parasitic Extraction, Running EM/IR ,Post Layout timing closure and Sign off (LVS,DRC,ERC,IR,Antenna ,etc)
Scripting: Good knowledge of shell , Perl , Tcl scripting
Timing: Strong background in STA closure
Technologies Node: 5nm,7nm, 16nm,14nm, 55nm
Foundry: TSMC , samsung, UMC
Managing team
Training new Team members
Low power design
Tools:
Synopsys:ICC2,Primetime,FC,StarRC,ICV
Candence:Innovus, and Tempus ,QRC
Caliber from Mentor graphics
Redhawk & RH-SC from Ansy