Suresh Kumar Kota

Product Engineer

Visakhapatnam, Andhra Pradesh, India2 yrs 2 mos experience

Highly Stable

Key Highlights

Experienced in VLSI and Design Verification.
Proficient in SystemVerilog and UVM methodologies.
Strong foundation in Digital Electronics and Logic Design.

Stackforce AI infers this person is a VLSI Design Verification Engineer with strong technical skills.

Contact

Skills

Core Skills

Design VerificationVlsi

Other Skills

DebuggingsimulationProject EngineeringProduct DesignUniversal Verification Methodology (UVM)SVVery-Large-Scale Integration (VLSI)Static Timing AnalysisLintAssertionsHVLDigital LogicRTL DesignLogic DesignDigital Electronics

Experience

2 yrs 2 mos

Total Experience

2 yrs 2 mos

Average Tenure

2 yrs 2 mos

Current Experience

Tech mahindra cerium pvt ltd

Design Verification Engineer

Apr 2024 – Present · 2 yrs 2 mos · Visakhapatnam, Andhra Pradesh, India · On-site

DebuggingsimulationProject EngineeringProduct DesignUniversal Verification Methodology (UVM)SV+18

Maven silicon

Trainee

Mar 2023 – Mar 2024 · 1 yr · Bengaluru, Karnataka, India · On-site

VerilogLinux

Education

MVGR College of Engineering

Bachelor of Technology - BTech — Electronics and communication engineering

Aug 2019 – May 2023

Sri Chaitanya College of Education

Intermediate — MPC

Jun 2017 – Mar 2019

Mrs.Mariadas Secondary School

Xth — ICSE

Jun 2016 – Apr 2017

Stackforce found 100+ more professionals with Design Verification & Vlsi

Explore similar profiles based on matching skills and experience

Rajendra Prasad

R&D Engineering Director

at Synopsys Inc

Mountain View, United States27 yrs 2 mos exp

ManagementMachine LearningLeadershipCustomer EngagementPeople Management

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp

Physical DesignMicroarchitecture

Prakash Mishra (प्रकाश मिश्रा)

Staff Engineer

at Synopsys Inc

Hyderabad, India7 yrs 11 mos exp

Analog Circuit DesignLow-power Design

Shubham Yadav

Senior Design Engineer

at Synopsys Inc

Bengaluru, India4 yrs 2 mos exp

Standard Cell Layout DesignPhysical DesignLayout Design

Ajitesh Mishra

Senior Engineer

at Sandisk

Bengaluru, India7 yrs exp

Application-Specific Integrated Circuits (ASIC)Hardware EngineeringFunctional VerificationSAPDevOps

Akshay Kinake

Staff Signoff Application Engineer

at Synopsys Inc

Bengaluru, India3 yrs 11 mos exp

Full Chip timing signoffSMC 3DIC STATiming ClosurePerformance Optimization

Lovleen Arora

Principal Engineer, NAND SubSystem Device Engineering

at Western Digital

Bengaluru, India9 yrs exp

NAND Flash MemorySystem DesignProduct Development

Allen Nguyen

SOC Physical Design Engineer

at Synopsys Inc

Ho Chi Minh City, Vietnam5 yrs 3 mos exp

Physical DesignApplication-Specific Integrated Circuits (ASIC)