Deeksha Mishra — Product Manager
# GPIO Library development. # Highly motivated custom/IO layout Engineer with 4+ years of experience. # Good understanding of DRC, and LVS. # Knowledge of Antenna, Latchup, Electromigration, Fingering, Matching, and Shielding. # Worked on the floor plan, placement, and routing of blocks like the level shifter, pre-driver, driver, transmitter, receiver, and logic etc. # Worked on Layout Verification and Reliability Verifications like ESD/PERC, EMIR, HV DRCs. # Hands-on experience with Synopsys Custom Compiler and Cadence Virtuoso tools in GF 22nm, IFS 16nm, TSMC 5nm, TSMC 2nm, and Rapidus 2nm technology nodes. # Good problem-solving skills, and analytical thinking.
Stackforce AI infers this person is a VLSI design engineer with expertise in analog and mixed signal layout.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 5 mos
Skills
- Layout Design
- Custom Compiler
- Analog And Mixed Signal Layout Design
- Analog Layout Design
- Vlsi Design
Career Highlights
- 4+ years of experience in layout design engineering.
- Expertise in VLSI and analog layout design.
- Hands-on experience with leading design tools.
Work Experience
Accenture
Silcon Engineering Senior Analyst (4 mos)
Synopsys Inc
Layout Design Senior Engineer (1 yr 1 mo)
A&MS Layout Design Engineer I (3 yrs 1 mo)
Indraprastha Institute of Information Technology, Delhi
Student Mentor (11 mos)
North Central Railway
Summer Trainee at North Central Railways (1 mo)
Motilal Nehru National Institute Of Technology
Summer Training Program on VLSI Design & Embedded System (VDES-2017) (1 mo)
Indian Institute Of Information Technology
Inspire Internship Program 2013 held under 6th Science Conclave (0 mo)
Education
M.Tech at Indraprastha Institute of Information Technology, Delhi
B.Tech at Institute of Engineering and Rural Technology (IERT), Prayagraj
Intermediate at BBS Inter College
High School at BBS Inter College
