Kirti Sikri Desai

Product Engineer

Bengaluru, Karnataka, India27 yrs experience
Highly Stable

Key Highlights

  • 20+ years of EDA industry experience
  • Award-winning technical author on Allegro SKILL programming
  • Cadence Luminary Winner 2022
Stackforce AI infers this person is a Senior Application Engineer specializing in EDA automation solutions.

Contact

Skills

Core Skills

Allegro PcbProcess Optimization

Other Skills

Allegro SKILLTCLVisual C++C++PerlEDAVerilogASICVLSIDebuggingFPGAAlgorithmsSoCSystemVerilogC

About

Transforming Package and PCB design workflows through advanced Allegro and APD automation solutions. As a Sr Principal Application Engineer at Cadence with 20+ years in the EDA industry, I specialize in creating custom solutions that streamline design processes. My expertise spans: 🔧 Technical Leadership: Leading complex projects in SKILL(Allegro , CM, VIrtuoso), Python, TCL scripting, and C++ development 📈 Process Optimization: Delivered automation tools that reduced design cycle time across multiple projects ✍️ Industry Thought Leadership: Published award-winning technical articles on Allegro SKILL programming and EDA methodologies, recognized by EDA Cafe 🏆 Recognition: Cadence Luminary Winner 2022, Sustainability Champion, and EDA Cafe article winner 🎯 Customer Success: Extensive experience helping customers optimize their Allegro workflows through custom solutions and technical guidance 🎤 Communication Excellence: Active Toastmaster developing leadership skills; IEEE Winteccon TPC member contributing to industry advancement Beyond technical expertise, I'm passionate about sharing knowledge through technical writing and mentoring teams to bridge complex engineering solutions with business outcomes. Core Technologies: Allegro PCB, APD, SKILL, Python, TCL, C++, Perl, SystemVerilog,

Experience

27 yrs
Total Experience
7 yrs 1 mo
Average Tenure
5 mos
Current Experience

Cadence design systems (india) pvt. ltd.

2 roles

Application Engineer Architect

Jan 2026Present · 5 mos

Sr Principal Application Engineer

Jul 2021Jan 2026 · 4 yrs 6 mos

Cadence design systems

3 roles

Sr Principal Application Engineer

Promoted

Jul 2022Jan 2026 · 3 yrs 6 mos

Principal Application Engineer

Jul 2017Jun 2022 · 4 yrs 11 mos

  • Projects in Allegro SKILL, TCL for MSA and contribution to COS, Collaboration and Team work
Allegro SKILLTCLAllegro PCBProcess Optimization

Lead Application Engineer

Nov 2013Jun 2017 · 3 yrs 7 mos

  • Work in Allegro PCB Front and Back End.
  • Successfully delivered projects using Allegro SKILL for GUI, Scripts.
  • Successfully delivered project using TCL for Orcad.
  • Successfully delivered license wrapper project using Visual C++
Allegro SKILLTCLVisual C++Allegro PCBProcess Optimization

Softjin infotech pvt ltd

Consultant

Aug 2001Jul 2013 · 11 yrs 11 mos

Softjin technologies

2 roles

Consultant

Aug 2001Jul 2013 · 11 yrs 11 mos

  • I have contributed to developing products and providing services by learning quickly, being versatile, taking on various roles of development, testing, release. My specific contributions are:
  • Testing GUI for Real Intent Meridian™ Clock Domain Crossing (CDC) debugging verification flow using Qt on Linux , 6 months (Feb 2012 - Current)
  • Programming Flash memories in Boundary Scan methodology using C++ on Windows , Test Softjin’s Static Timing Analysis Engine Using SoftJin’s Automated Test and Regression Environment in Perl on Linux and Windows
C++Perl

Consultant

Aug 2001Jul 2013 · 11 yrs 11 mos

Cadence design systems

Software Engineer

Jun 1995Jan 1998 · 2 yrs 7 mos · Noida, Uttar Pradesh, India

  • Worked on Checkplus and writing Verilog modules

Education

Birla Institute of Technology and Science, Pilani

Bachelor's degree — Mech & EEE

Jan 1990Jan 1995

CJM DehraDoon

X and XII

Jan 1979Jan 1991

Stackforce found 100+ more professionals with Allegro Pcb & Process Optimization

Explore similar profiles based on matching skills and experience