Rahul shantagiri

Software Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in EDA automation and verification tools.
Led critical projects for major semiconductor companies.
Strong background in Python and C++ development.

Stackforce AI infers this person is a Semiconductor Software Engineer with expertise in EDA tools and verification systems.

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Skills

Core Skills

Eda Flow AutomationFormal VerificationProtocol DebuggingVerification ToolsDebug Tools

Other Skills

PythonFlaskPostgreSQLHTMLJinja2GrafanaTCLShellC++QTNLPData StructuresAlgorithmsSQLC

Experience

8 yrs 8 mos

Total Experience

3 yrs 4 mos

Average Tenure

1 yr 11 mos

Current Experience

Arm

Senior Software Engineer (L4)

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

At Arm, I work at the intersection of EDA automation and data-driven verification visibility, focusing on tools and flows that accelerate chip design and sign-off.
Owning and developing the Formal Sign-off / Tapeout Dashboard, a critical platform used in Arm’s first SoC tapeout — Phoenix SoC.
Designed a Python-based data extraction layer that parses and aggregates Formal Verification (FV) and LEC results from multiple design stages.
The extractor layer feeds structured data into a PostgreSQL database, enabling efficient storage and traceability of verification metrics.
Built the dashboard’s Flask backend and HTML-Jinja frontend, delivering a seamless and interactive web interface for verification and design engineers.
Provides real-time visibility into sign-off status, highlighting whether each IP or subsystem is ready for tapeout or requires further verification.
Automated multiple EDA flows involving Cadence and Synopsys tools across stages such as Synthesis, PnR, Pre-CTS, Design Finishing, and STA.
Developed custom scripts in Python, TCL, and Shell to drive consistency, reproducibility, and faster turnaround in verification and implementation flows.
The platform significantly reduces manual validation, improves sign-off predictability, and enhances cross-team transparency.
Integrated Grafana dashboards to monitor runtime metrics, system health, and data pipeline efficiency.
Collaborate with design, formal, and flow automation teams to continuously expand dashboard coverage to new verification domains.
Contribute to the development of reusable frameworks for data extraction, log parsing, and constraint validation within Arm’s EDA ecosystem.
Championing best practices for data integrity, flow reliability, and scalable verification infrastructure across projects.
Tech Stack: Python, Flask, PostgreSQL, HTML, Jinja2, Grafana, TCL, Shell
Domain Expertise: EDA Flow Automation, Formal Verification, LEC, Sign-off & Tapeout Systems

PythonFlaskPostgreSQLHTMLJinja2Grafana+4

Synopsys inc

4 roles

R&D Engineer, Sr I

Promoted

Dec 2023 – Jun 2024 · 6 mos

I am currently spearheading the development of transaction-level debugging for a protocol suite under the VERDI automated debug platform, leveraging a tech stack that includes C/C++, the QT GUI framework, Python, and NLP (Natural language processing). This platform is extensively utilized in the verification of IC chips and has gained prominence among major semiconductor giants such as Intel, Qualcomm, NVIDIA, and Samsung

C++QTPythonNLPProtocol DebuggingVerification Tools

R&D Engineer, II

Nov 2020 – Dec 2023 · 3 yrs 1 mo

I was involved in development of tool used in verification of testbench environment named VERDI tbAutoRCA, Developed using C++ with QT GUI framework, python and Natural language processing (NLP).

C++QTPythonNLPVerification Tools

R&D Engineer

Apr 2018 – Nov 2020 · 2 yrs 7 mos

I was owning one of the debug tool under verdi debug platform known as verdi performance analyzer which is developed with C++ and QT. which is used to calculate the performance of system on chip.
used by customer like Intel, Nxp , Amazon, Samsung, gaudi labs etc

C++QTDebug Tools