Nagarjuna Goranti — Software Engineer

I am a Design Verification Engineer at Synopsys specializing in ASIC/SOC functional verification, UVM-based testbench architecture, formal verification, and high-performance simulation optimization for complex multi-IP semiconductor designs. My expertise spans coverage-driven verification (CDV), constrained random verification, assertion-based verification (SVA), and formal property verification (FPV) with strong exposure to RTL/GLS convergence, regression optimization, and silicon validation workflows. I focus on solving real-world verification challenges such as simulation bottlenecks, coverage closure gaps, race conditions, debug complexity, and regression scalability issues in large SoC environments. At Synopsys, I contribute to validation of next-generation VCS simulation technologies, working closely with R&D and FAE teams to improve tool robustness, debugging efficiency, and customer design stability. Key impact: • 3.5x performance improvement in RTL/GLS verification environments • 2.5x runtime reduction using DPO and 2.3x gains using Jaguar flows • Coverage improvement from 82% → 100% using VC Formal (FCA) • 900+ verification/tool issues resolved across customer + internal environments • Built scalable UVM environments (RAL, scoreboards, callbacks, error injection) • Strong exposure to AXI/APB, CDC/RDC, lint signoff, and UPF low-power flows I am passionate about building scalable verification systems that accelerate silicon readiness and enable first-pass silicon success.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC/SOC functional verification.

Location: Hyderabad, Telangana, India

Experience: 8 yrs