Emarishi Kataria — Product Engineer

Hello all! I'm Emarishi Kataria, Did my Master's from IGDTUW'23 with a specialization in VLSI(Very large scale integration) design. Technical Skills • HDL: Verilog Programming including Advanced Verilog and Code Coverage • HVL: System Verilog • Verification Methodologies: Constraint Random Coverage Driven Verification, Assertion Based Verification • TB Methodology: UVM • EDA Tool: EDA playground,Mentor Graphics - Questasim • Domain: ASIC/FPGA front-end Design and Verification • Operating System: Linux As I have pursued a career in VLSI, I also have an extensive knowledge of System Verilog Assertions,Coverage,and Randomization,UVM,and STA,Digital Electronics, RTL coding, Verilog. I do have a good understanding of Op-Amp, BGR & Folded Cascode op-amp as I have worked on Special Man power development project in collaboration with IIT Delhi. Add on to that I know C/C++, Python worked on DB browser, Perl language. I did UART project using Verilog Recently, published a paper on materials using DFT technique in NIT Jalandhar of Springer, Electrical chapter notes, Scopus Indexed I'm Passionate about innovation and staying updated with the latest advancement in the VLSI field. I constantly seek opportunities to learn and grow in the VLSI domain with a good problem solving skills and collaborative mindset.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC/FPGA front-end design and verification.

Location: New Delhi, Delhi, India

Experience: 2 yrs 10 mos