Yi-Ping Pan

Senior Software Engineer

Taipei, Taipei City, Taiwan4 yrs 6 mos experience

Key Highlights

Achieved 99.8% runtime reduction in critical designs.
Expert in Compiler Technology and EDA Toolchain Optimization.
Specializes in modernizing legacy architectures using advanced techniques.

Stackforce AI infers this person is a high-performance EDA engineer specializing in compiler optimization and system architecture.

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Skills

Core Skills

Compiler Architecture & OptimizationPerformance EngineeringSystem Reliability

Other Skills

High-Performance Computing (HPC)Parallel ProgrammingVHDLMLIRCompiler OptimizationIR-level algorithmsParallel Compilation FrameworkCustom artifact cachingPre-compiled Headers (PCH)Root cause analysisSystematic bisect methodologiesVery-Large-Scale Integration (VLSI)Communication TheoryElectrical EngineeringSignal Processing

About

System Software Architect bridging the gap between Hardware Semantics and Software Design. With 3+ years of deep-dive experience in Compiler Technology (VHDL/LLVM) and EDA Toolchain Optimization, I specialize in solving system-level performance bottlenecks that others find "impossible." My expertise lies in modernizing legacy architectures by applying Functional Programming concepts (Haskell/SICP) and Data-Oriented Design to industrial-scale C++ codebases. I don't just write code; I design systems. Whether it's achieving a 99.8% runtime reduction for critical simulation flows or engineering automated stability frameworks, I believe in the power of abstraction and precision. Core Focus: 🔹 Compiler Architecture & Optimization (LLVM, MLIR) 🔹 Modern C++ (C++20, TMP, Memory Layout) 🔹 Hardware Description Languages (VHDL LRM, Verilog) 🔹 System Reliability & Automated Triage Always exploring the intersection of rigorous theory (Type Theory) and pragmatic engineering.

Experience

4 yrs 6 mos

Total Experience

Average Tenure

Current Experience

新思科技

Senior Software Engineer

Nov 2021 – May 2026 · 4 yrs 6 mos · Taiwan · On-site

Architectural Modernization & MLIR Initiative:
Conducted deep-dive analysis on legacy VHDL elaboration bottlenecks. Investigated MLIR-based dialect strategies to address state explosion, formulating a modernization proposal to decouple semantic analysis from structural flattening via aggressive partial evaluation.
Performance Engineering:
Achieved a landmark 99.8% runtime reduction (25h to 12m) on critical industrial designs by redesigning core IR-level algorithms and implementing a parallel compilation framework (60% speedup).
Incremental Compilation Framework:
Engineered a scalable incremental build system unifying four distinct flows. Introduced custom artifact caching and Pre-compiled Headers (PCH), fundamentally improving artifact reuse for complex SoCs.
Regression Ownership & Critical Issue:
Resolution Owned the stability of 6,000+ daily regression tests. Spearheaded the root cause analysis for complex failures (e.g., platform-specific memory corruption) by applying systematic bisect methodologies to isolate regressions in the massive VHDL codebase. Successfully resolved critical blockers for top-tier customers (Nokia, AMD), significantly reducing resolution time.

High-Performance Computing (HPC)Parallel ProgrammingCompiler Architecture & OptimizationPerformance Engineering