Nagesh N Nazare

Software Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience

Key Highlights

Expert in hardware development and FPGA integration.
Strong background in Linux systems and multithreading.
Proven track record in enhancing runtime performance.

Stackforce AI infers this person is a Semiconductor and Electronics expert with strong software development skills.

Contact

Skills

Core Skills

RuntimeMultithreadingC++Xilinx VivadoSchematic Design

Other Skills

ScalabilityTCLZynq 7000 FPGARTL designLinuxSatellite Communications (SATCOM)Computer NetworkingCUDAData StructuresAlgorithmsNeural NetworksMachine LearningGNU DebuggerValgrindGit

About

Strong knowledge in: - Hardware development & board bring up of Xilinx Zynq 7000 series SoC. - Linux System calls, processes, files and inter-process communication. - Multithreading and Concurrency - Communication Protocols such as UART, SPI, I2C, EtherCAT. - Programming with C, C++ - Debugging with gdb, valgrind. - Makefiles & Build-systems like Auto-tools and CMake - Scripting with Python, Bash and Javascript. - Markup with HTML, CSS. - Version Control with Git and Perforce. - Containerisation with Docker - net-snmp & netconf - Software tools such as GNU-Octave, Matlab/ Simulink, Vivado and Petalinux.

Experience

7 yrs 10 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

3 roles

Staff Engineer, R&D Engineering

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · On-site

Runtime performance and Scalability Enhancements for Design Compiler NXT / Fusion Compiler
Non-Physical Flow / WLM

RuntimeMultithreading

Sr Engineer, R&D Engineering

Promoted

Feb 2024 – Feb 2025 · 1 yr · Bengaluru, Karnataka, India · On-site

Sequential Mapping
DCNXT Timer

RuntimeMultithreading

R&D Engineer, II

Sep 2022 – Feb 2024 · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

C++TCL

Bharat electronics limited

2 roles

Deputy Engineer (R&D)

Promoted

Apr 2019 – Aug 2022 · 3 yrs 4 mos · Bangalore

My responsibilities include:
End-to-end ownership of the product design cycle.
System-level product architectural and algorithmic design.
Schematic Design for Hardware
RTL design and IP integration in the FPGA based development cycle.
Building Linux from source and porting the firmware on the custom hardware with required peripheral communication drivers in kernel space.
Building Device tree blob for the hardware interfaces.
Software development of EtherCAT communication protocol based motor-drive control master on x86 and ARM-based systems.
Preparation and review of test specifications, test strategies and test cases.
Analyze problems, provide a suitable solution and speculate changes in the design.

Xilinx VivadoZynq 7000 FPGA