Mahalakshmi Boominathan — Software Engineer

Senior Design Verification Engineer with strong experience building and running verification environments for complex digital designs. Comfortable working with SystemVerilog and UVM, with a focus on writing scalable, reusable components and maintaining efficient workflows. Key strengths include: • Development of Universal Verification Components (UVCs) based on detailed specifications • Experienced in creating block-level verification environments for a variety of design blocks • Proficient in the complete verification cycle — from creation of the verification plan (vPlan) to achieving coverage closure • Writing and implementing block-level and system-level test cases • Creating scoreboards and functional coverage models to ensure thorough verification • Hands-on experience in DPI calls and integrating high-level models into test benches • Well-experienced in using industry-standard simulation tools for efficient debugging and regression testing • In-depth knowledge of standard interfaces and protocols including AMBA AXI, APB, I2C, and SPI • In-depth knowledge of standard redundancy protocols (HSR/PRP)

Stackforce AI infers this person is a Design Verification Engineer in the Semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 9 mos