Sagar Kumar Lo

Software Engineer

South 24 Parganas, India4 yrs 11 mos experience
Highly Stable

Key Highlights

  • Lead Analog Design Engineer with extensive experience.
  • Strong foundation in VLSI and Analog Design.
  • Proven ability to manage multiple tasks effectively.
Stackforce AI infers this person is a VLSI and Analog Design Engineer with a focus on renewable energy projects.

Contact

Skills

Other Skills

Problem SolvingDesignCommunicationPresentationsLayout DesignDesign Engineering

About

Seeking a challenging position in an esteemed organization that will utilize my abilities and experience for achieving the growth and success of organization while concurrently offering me opportunities for career advancement. Willingness to learn new things and ability to manage multiple tasks at one time

Experience

4 yrs 11 mos
Total Experience
2 yrs 1 mo
Average Tenure
8 mos
Current Experience

Cadence

Lead Analog Design Engineer

Oct 2025Present · 8 mos · India

Synopsys inc

2 roles

Senior Analog Design Engineer

Promoted

Jan 2024Oct 2025 · 1 yr 9 mos

Analog Mixed Signal Design Engineer

Aug 2022Jan 2024 · 1 yr 5 mos

Hcl engineering and r&d services

2 roles

Member Of Technical Staff (Sankalp Semiconductors)

Jul 2021Aug 2022 · 1 yr 1 mo · Kolkata, West Bengal, India

VLSI Design Associate Intern at HCL Technologies

Dec 2020Jul 2021 · 7 mos · Kolkata, West Bengal, India

  • Working on AFE Design at HCL Technologies

Ardent computech pvt ltd

Data Science and Machine Learning Using Python

May 2020Jun 2020 · 1 mo · Kolkata, West Bengal, India

  • Completed a project on the prediction of solar power. The project predicts the amount of solar power that can be generated at a particular location by studying the physical conditions of that place. This can be beneficial for various institutions to plan for green energy.

Coursera

2 roles

Introduction to Data Science in Python

May 2020Jun 2020 · 1 mo

Data Science Math Skills

May 2020Jun 2020 · 1 mo

Electronic center of excellence

VLSI Design Engineer

Dec 2019Jan 2020 · 1 mo · Bhubaneshwar, Orissa, India

  • 200 hours of extensive VLSI design training with knowledge of FPGA, Cadence, and Mentor Graphics.
  • The course was based on schematic and layout design.

Education

Heritage Institute of Technology

B.Tech — Electronics and Communications Engineering

Jan 2017Jan 2021

B.D.M. International School

Higher Secondary School Certificate — Science

Apr 2015Apr 2017

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