Anurag Shakya

Software Engineer

Bengaluru, Karnataka, India3 yrs 6 mos experience

Most Likely To Switch

Key Highlights

Expert in C++ and SystemVerilog for semiconductor design.
Proven track record in optimizing chip design flows.
Strong academic foundation in Computer Science.

Stackforce AI infers this person is a Semiconductor R&D Engineer with expertise in RTL and SystemVerilog.

Contact

anuragshakyaofficial@gmail.com LinkedIn

Skills

Core Skills

SystemverilogRtlC++

Other Skills

Power, Performance, and Area (PPA) optimizationJIRAAutomationGitHub CopilotUPFSAIFPythonCJavaAlgorithmsData StructuresWeb DevelopmentHTMLCascading Style Sheets (CSS)SQL

About

Senior Research and Development Engineer at Synopsys Inc with expertise in C++, Linux, TCL, and SystemVerilog. Graduated with an MTech in Computer Science from Indraprastha Institute of Information Technology, Delhi, in 2023, building a strong academic foundation for solving complex engineering challenges. At Synopsys, contributed to advancing R&D processes by leveraging technical skills and collaborating on innovative solutions. Motivated to apply technical expertise and academic background to drive impactful contributions in the field of computer science and engineering.

Experience

3 yrs 6 mos

Total Experience

1 yr 9 mos

Average Tenure

2 yrs 11 mos

Current Experience

Synopsys inc

4 roles

Sr, Research & Development Engineer

Jan 2026 – Present · 5 mos

Senior Research And Development Engineer

Promoted

Dec 2024 – Jan 2026 · 1 yr 1 mo

Spearheaded the successful implementation of the Port Naming Customization feature (supporting receiver-based, driver-based, direction-based, and combined methods), achieving a 99% alignment rate for port names between the restructured RTL and the gate-level netlist.
Worked in the Toplevel Interconnect Planning (TIP) feature, automating the insertion of feedthrough connections to effectively minimize signal delays in complex designs.
Contributed in optimization of chip design flow by implementing ”Grouping of Multi-Instantiated Modules (MIM)" feature, achieving an 85% reduction in RTL module count and decreasing production costs by up to 30% while ensuring logical equivalence.
Resolved multiple customer-reported JIRA tickets for enhancing the RTL Architect (RTLA) tool’s restructuring capabilities, with a specific focus on optimizing Power, Performance, and Area (PPA) aware RTL editing and restructuring.

SystemVerilogRTLPower, Performance, and Area (PPA) optimizationJIRAAutomation

R&D Engineer I

Jul 2023 – Dec 2024 · 1 yr 5 mos

Resolved quality JIRA tickets for enabling a combined restructuring flow within the RTL Architect (RTLA), integrating RTL, UPF (Unified Power Format), and SAIF (Switching Activity Interchange Format) for comprehensive design optimization.
Utilized GitHub Copilot as a productivity aid to generate automation scripts for updating failed regression test cases, improving efficiency while maintaining focus on enhancing overall code quality.

RTLGitHub CopilotUPFSAIF

Graduate Engineering Trainee

Jan 2023 – Jul 2023 · 6 mos

Spearheaded the migration from Python to C++ for all reporting application within GenSys product.
Resolved internal quality Jiras to enhance the product’s overall stability.

C++PythonJIRA