A

Archana Pandeshwar

Software Engineer

Bengaluru, Karnataka, India2 yrs 10 mos experience

Key Highlights

  • Currently an Asic Digital Design Engineer at Synopsys Inc.
  • Interned at Synopsys Inc. focusing on Verilog and RTL Design.
  • Graduated with a Bachelor's degree in Electrical Engineering.
Stackforce AI infers this person is a Digital IC Design Engineer with experience in semiconductor design.

Contact

LinkedIn

Skills

Core Skills

Digital Ic Design

Other Skills

VerilogRTL Design

Experience

2 yrs 10 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

2 roles

Asic Digital Design Engineer

Aug 2023 – Present · 2 yrs 10 mos · India

Digital IC DesignVerilogRTL Design

Technical Intern

Mar 2023 – Jul 2023 · 4 mos · India

VerilogRTL Design

Education

B. M. S. College of Engineering

Bachelor's degree

Jan 2019 – Jan 2023

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