Sridhar Pokala

Software Engineer

Sheffield, England, United Kingdom11 yrs 9 mos experience

Highly Stable

Key Highlights

12 years of experience in VLSI physical design.
Expert in RTL2GDS execution across multiple nodes.
Led teams in timing and reliability for complex designs.

Stackforce AI infers this person is a VLSI Physical Design Engineer with extensive experience in semiconductor design and implementation.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

RTL2GDStiming closureflow developmentRTL-GDS executiontimingreliabilityfloorplanVHDLMicrosoft OfficeProgrammingPerlCadence VirtuosoEmbedded SystemsCMatlab

About

• ~12 yrs of experience in block/subsystem execution ranging from RTL2GDS. • Have a clear understanding and execution experience on Synthesis, Floorplan, Place, CTS, Routing, PV ,STA and EMIR. • Worked on Intel Integrated GPU blocks which have GC as big as 1.5+M and dealt with placement, routing and crosstalk challenges. • Worked on many Cadence SerDes IPs / Test chips with critical turnaround times. • Worked on block and subsystem implementation & signoff of Network Processor Unit Chips. • Apart from block level, handled chip level tasks and led a team aswell. • Familiar with Both Cadence/Synopsys Tools • Experienced in developing Tcl, Sh, PERL scripts to avoid redundant manual tasks • Worked on multiple nodes : 5nm,7nm,12nm,16nm TSMC; 10nm,14nm Intel; 8nm,28nm Samsung; 14nm Global Foundries • I am a good team player and believer of open door policy • Apart from the profession, I enjoy cricket, tennis, football and movies.

Experience

11 yrs 9 mos

Total Experience

2 yrs 11 mos

Average Tenure

2 yrs 11 mos

Current Experience

Arm

Staff Implementation Engineer

Jul 2023 – Present · 2 yrs 11 mos · Sheffield, England, United Kingdom · On-site

Ydesign ab

2 roles

ASIC Backend Engineer

Jan 2021 – Jul 2023 · 2 yrs 6 mos

ASIC Physical Design Engineer

Dec 2019 – Jan 2021 · 1 yr 1 mo

Worked as a consultant from Swedium Global Services AB. During this period , I worked on a network chip in TSMC 16ffc node. Responsible for RTL2GDS implementation of high GC blocks with full of Memories along with subsystem level timing closure and flow development tasks.

RTL2GDStiming closureflow developmentPhysical DesignVLSI

Cadence design systems

2 roles

Lead Physical Design Engineer

Jul 2018 – Dec 2019 · 1 yr 5 mos

Senior Physical Design Engineer

Jul 2016 – Jul 2018 · 2 yrs

During this period, I got a chance to work on multiple SerDes IPs and exposed to multiple TSMC nodes from 16nm -7nm. Main challenge being the project timelines and the design inputs, learnt collaborating with other teams and converged blocks with extra efforts. Also got a chance to work on some chip level tasks

Intel corporation

Component Design Engineer

Jul 2013 – Jun 2016 · 2 yrs 11 mos · Bengaluru, Karnataka, India

During this period, I worked in physical design team. I was responsible for RTL-GDS execution of blocks varying across latest process nodes using the Synopsys tools like Design Compiler,IC compiler and Primetime SI. Along with execution, led a set of people in Timing,Reliability and Floorplan perspective at section level.

RTL-GDS executiontimingreliabilityfloorplanPhysical DesignVLSI