Syed Razeen Raj Mohamed

CEO

Milpitas, California, United States16 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Signal Integrity for high-speed designs.
Proven track record in multi-gigabit link simulations.
Strong collaboration with vendors for design improvements.

Stackforce AI infers this person is a Signal Integrity Engineer specializing in high-speed computer networking solutions.

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Skills

Core Skills

Signal IntegrityDesignAntenna Design

Other Skills

Evaluation of 56G SERDESDesign and validation of line cardsDebugging failuresVendor collaborationDebuggingValidationSignal Integrity simulationDesign of test cardsGuidelines for signal qualitySignal Integrity analysisDesign of launch structuresStack up planningPower Integrity AnalysisEMI/EMC AnalysisGSM

About

Experienced Signal Integrity Engineer with a demonstrated history of working in the computer networking industry. Skilled in Design, Debugging, Simulations and validation. - Simulation and Characterization of Multi-Gigabit serial links up to 56Gbps. - Analysis of parallel interfaces DDR3, DDR4 QDRII. - Well versed in characterization of Optical links. - Skilled in using lab measurement equipment such as Sampling scopes, Real time scopes, BERT, Spectrum Analyzer, VNA, TDR. - Have used ADS, Ansoft HFSS, Sisoft QCD and QSI, PowerDC, PowerSI, Ansoft Designer, Mentor Hyperlynx for Simulations!!

Experience

16 yrs 11 mos

Total Experience

5 yrs 2 mos

Average Tenure

10 yrs 8 mos

Current Experience

Cisco

5 roles

Principal Hardware Engineer

Jan 2026 – Present · 5 mos

Leader

Promoted

Dec 2022 – Present · 3 yrs 6 mos

Leader

Promoted

Dec 2021 – Dec 2022 · 1 yr

Technical Lead

Jun 2021 – Dec 2021 · 6 mos

Signal Integrity Engineer

Oct 2015 – Jun 2021 · 5 yrs 8 mos

Evaluation of the 56G SERDES from multiple vendors for its BER performance with the current and next generation backplane. Key member in concluding if the next generation line card, fabric card can be used with legacy backplane.
Key member in the selection of the FPGA for a next generation line cards. Involved in assigning the SERDES pins for FPGA, connector and did exhaustive layout feasibility.
Worked with the vendor on the development of the optics enabling the multi-chassis configurations. Debugged the failures and provided suggestions to the vendor for improving the design. Provided suggestions to implement screening to improve the yield and performance.
Involved in the design and validation of the line cards and fabric cards for multi chassis configurations. Involved in the architecture discussion for the next generation line cards.

Signal IntegrityEvaluation of 56G SERDESDesign and validation of line cardsDebugging failuresVendor collaborationDesign

Juniper networks

Hardware Engineer 3

Jul 2013 – Oct 2015 · 2 yrs 3 mos · Bangalore

Signal integrity simulation & validation for high end routers and switches. Providing guidelines & constraints to ensure Signal quality & timing.
Design of test cards, which will be used for the qualification of materials to be used in the next generation routers and switches. Analysis includes the design of Launch structures for the connectors, Stack up planning and measurements.

Signal Integrity simulationValidationDesign of test cardsGuidelines for signal qualitySignal IntegrityDesign

Hcl technologies

Signal integrity, Power Integrity and EMI/EMC Analyst and Antenna Design and Testing

Jul 2009 – Jul 2013 · 4 yrs

Design and testing of the Base station antenna. Have designed and tested adjustable phase shifter for BST for GSM800, GSM 1710 and Wimax bands. Have done High Speed Signal Integrity analysis for Multilple boards that runs a speed upto 10G.Power Integrity Analysis and EMI EMC Analysis

Signal Integrity analysisDesign of launch structuresStack up planningSignal IntegrityDesign