Gaurav Jain

Product Manager

Bengaluru, Karnataka, India15 yrs 2 mos experience

Key Highlights

Expert in SOC Power Integrity and Reliability.
Proven track record in leading high-performance teams.
Skilled in developing methodologies for PDN Flow.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Power Integrity and Reliability for AI and HPC.

Contact

Skills

Core Skills

Power IntegritySoc SignoffVlsiPhysical VerificationStatic Timing AnalysisPhysical Design FlowFloorplanningSignal Integrity Analysis

Other Skills

ReliabilityPDN Flow developmentPDNIR analysisPad ring creationPower PlanningPlacementClock Tree SynthesisRoutingFunctional ECO implementationAnalog routingDebugging toolsDesign issuesElectronmigrationTeam Building

About

Dynamic Sr Manager & Tech Leader with a strong background in Physical Design & PDN Signoff, Methodology Development, Process Improvement and leading high-performance team

Experience

15 yrs 2 mos

Total Experience

Average Tenure

Current Experience

Nextsilicon

Senior Physical Design Engineer

May 2025 – Present · 1 yr 1 mo · Bengaluru · Hybrid

Leading Power Integrity and Reliability for AI and HPC products. Responsible for PDN Flow development, Methodologies and SOC Signoff.

Power IntegrityReliabilityPDN Flow developmentSOC Signoff

Qualcomm

5 roles

Sr. Staff Engineer/ Manager

Dec 2022 – May 2025 · 2 yrs 5 mos

VLSISOC SignoffPDN

Staff Engineer/Manager

Aug 2021 – Nov 2022 · 1 yr 3 mos

Staff Engineer

Dec 2019 – Jul 2021 · 1 yr 7 mos

Sr. Lead Engineer

Promoted

Apr 2017 – Nov 2019 · 2 yrs 7 mos

Engineer II

Apr 2015 – Mar 2017 · 1 yr 11 mos

Megachips-corporation

Design Engineer

Oct 2014 – Apr 2015 · 6 mos · Bengaluru Area, India

Worked on various technology nodes, including 28nm, 40nm, 55nm, and 65nm, during a short duration.
Specialized in Physical Verification, IR analysis (Static and Dynamic), and Static Timing Analysis (STA).

Physical VerificationIR analysisStatic Timing Analysis

Atmel corporation

2 roles

IC Designer

Promoted

Apr 2014 – Oct 2014 · 6 mos

Worked on the entire Physical Design flow, including Pad ring creation, Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Verification (DRC, LVS, XOR, PERC).
Conducted IR drop analysis, both Static and Dynamic.
Utilized tools such as Encounter Digital Implementation, Calibre, Apache Redhawk, and Virtuoso Layout.

Physical Design flowPad ring creationFloorplanningPower PlanningPlacementClock Tree Synthesis+2

Associate IC Designer

Aug 2012 – Mar 2014 · 1 yr 7 mos

Initially involved in functional and timing ECO implementation and Physical Verification using Virtuoso and Caliber.
Conducted full chip floorplanning, power planning, and Analog routing using Encounter.

Functional ECO implementationPhysical VerificationFloorplanningPower planningAnalog routing

Cadence design systems

Consultant

Oct 2010 – Jul 2012 · 1 yr 9 mos · Noida · On-site

Application Engineer, IC Design Team:
Supported customers in debugging tools and design issues, leveraging expertise in the latest Cadence Encounter Digital Implementation (EDI) and Encounter Timing System (ETS).
Proficient in handling various files such as LEF, LIB, SPEF, SDF, incremental SDF, and SDC.
Experienced in working on the Linux platform and proficient in TCL scripting.
Skilled in Verilog coding for preparing test cases.
FloorPlanning: Efficiently placed hard blocks using EDI.
Placement and Routing: Executed placement and various types of routing using trial router, nanorouter, and srouter.
Power Planning: Created power rings, stripes, and sroute.
Clock Tree Synthesis (CTS): Built and debugged clock trees.
Static Timing Analysis: Conducted analysis using EDI and ETS.
Signal Integrity (SI) Analysis: Performed glitch and noise analysis using EDI and ETS.
Signoff SI and Timing: Ensured signoff using ETS.
Multi-Mode Multi-Corner (MMMC) and Dynamic Multi-Mode Multi-Corner (DMMMC): Utilized in EDI and ETS.
Partitioning: Implemented hierarchical design flow.
Foundation Flow: Followed Cadence recommended flow for design in EDI and ETS.
Noise Characterization: Generated .cdb files using make_cdb utility on ETS.
Created Non-Default Rules (NDR) for design requirements.