ABHAY SONKER

DevOps Engineer

Delhi, India6 yrs 2 mos experience

Most Likely To Switch

Key Highlights

5+ years of experience in design verification.
Expertise in AMBA protocol development.
Strong background in SystemVerilog and UVM.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and digital design.

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Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

DebuggingVerilogVery-Large-Scale Integration (VLSI)Digital ElectronicsField-Programmable Gate Arrays (FPGA)C++Object-Oriented Programming (OOP)Data StructuresLinuxShell ScriptingVHDLTCLStatic Timing AnalysisCDCQuestaSim

About

I am a Design Verification Engineer with more than 5+ years of Industry Experience in VIP development and debugging, handling customer queries and DUT integration. I have worked on multiple protocols like CHI/AXI/Stream/Lite/ACE, USB4 V1 including HUB and Retimer. I graduated from BVCOE in 2021 - (Electronics and Communication Engineering)

Experience

6 yrs 2 mos

Total Experience

1 yr 6 mos

Average Tenure

1 yr 11 mos

Current Experience

Synopsys inc

Sr. Verification Protocol Solutions Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Development of Sequences/Testcases, Custom Testbenches, debugging and custom Testbench solution requirement from the user for AMBA CHI/DTI/AXI/ Stream/Lite protocol

DebuggingVerilogSystemVerilogVery-Large-Scale Integration (VLSI)Digital ElectronicsField-Programmable Gate Arrays (FPGA)+13

Truechip solutions

Design Verification Engineer

Jul 2022 – Jun 2024 · 1 yr 11 mos · Noida, Uttar Pradesh, India

SystemVerilogObject-Oriented Programming (OOP)

Marquee semiconductor inc.

Design Verification Engineer

Apr 2021 – Jun 2022 · 1 yr 2 mos · Bhubaneswar, Odisha, India

SystemVerilogObject-Oriented Programming (OOP)

3st technologies

Trainee

Feb 2020 – Apr 2021 · 1 yr 2 mos · Noida, Uttar Pradesh, India

Mentor Graphics Higher Education Program(HEP) for Digital Design Verification using System Verilog and UVM.

SystemVerilogObject-Oriented Programming (OOP)

Education

Bharati vidyapeeth college of engineering

Bachelor's degree

Jan 2017 – Jan 2021

Stackforce found 100+ more professionals with Systemverilog & Universal Verification Methodology (uvm)

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