Oct 2022 – Jan 2025 · 2 yrs 3 mos · On-site

Mar 2019 – Oct 2022 · 3 yrs 7 mos · Banglore

• ASIC Design Engineer.
• Part of PCIE Physical layer Design team

Jul 2015 – Mar 2019 · 3 yrs 8 mos · Chennai Area, India

• Roles and Responsibilities included,
• Contribution to Architecture Discussion and analysis.
• End to end module ownership and timely delivery of Salable, Debug friendly, Hardware efficient, quality modules.
• Micro Architecture design, RTL Implementation, Verification support and follow up, FPGA validation support, Timing Analysis, Power Analysis, STA Signoff, and ASIC Bringup support for all the owned modules
• Module Lead and Design Expert for Low Power Main Memory Controller.
• Responsible for Flash Memory Controller Feature enhancement.

Jan 2015 – May 2015 · 4 mos · Greater Chennai Area

• Automated blood sample analysis system was developed using a microscope fixed with CMOS camera module OV7670 and FPGA XC6SLX9.
• VHDL, JAVA and MATLAB was used to interface the components, analyse blood cells and display the results.

Jul 2014 – Aug 2014 · 1 mo · Greater Chennai Area

• Industrial internship with Programmable Logic Controller Team. Hands on Experience using PLC and coding for PLC.
• PLC ladder programming for real time applications using Zen Software were developed during the period of Internship.