Aug 2024 – Dec 2024 · 4 mos · Hyderabad, Telangana, India

Jun 2021 – Aug 2024 · 3 yrs 2 mos · Hyderabad, Telangana, India

• Part of the Bing.com team working on User alligned experiences.

Jun 2020 – Jun 2021 · 1 yr

• ● Complete Ownership of System Verilog to C++ Trans Compiler using Verific APIs which forms a crucial block in the Vivado SW tool used by customers to programme Xilinx FPGAs.
• ● Improved Xilinx TimeCap compiler supporting the Static Timing Analysis (STA) by reducing the runtime by 50% and memory by 2X.
• ● Extended Xilinx Verification tools to verify FPGA programming by taking Data oriented approach, which brought down the runtime by 5X compared to existing simulation based methodologies.
• ● Implemented checkers using Object Oriented Methodologies making it reusable and extensible. This resulted in early detection of 10+ Hardware bugs leading to productivity improvements.
• ● Served as goto expert on both internal and external technologies. Instrumental in developing training sessions and handling debugs.

Nov 2017 – Jun 2020 · 2 yrs 7 mos

Sep 2015 – Oct 2017 · 2 yrs 1 mo

Aug 2013 – Aug 2015 · 2 yrs · Bengaluru Area, India

• ● Complete Ownership of Clipper unit Validation in Fixed Function pipeline of Intel HD Graphics.
• ● Came up with Validation specification and Testplan in conjunction with multiple stakeholders.
• ● Developed new tests, both directed and random to attain maximum coverage there by giving high confidence.
• ● Delivered Bug Free code post freeze, which got recognition through Department Award.

Jul 2012 – Jul 2013 · 1 yr · Bengaluru Area, India

• ● Part of the team that works for commercialization of Modem Protocol with respect to Universal Integrated circuit card (SIM Card).
• ● Involved in the stabilization of UICC modules in various Upcoming and Existing Samsung Smart phone models.

Jul 2011 – Dec 2011 · 5 mos · Bengaluru Area, India

• Project title: Design of CPLD for Branch wireless controller
• Description: Worked in a team that designed a Wireless controller for Medium size offices. These controllers are instrumental in delivering security features and other enhancements for Wireless networks. I was entrusted with the designing of the CPLD required for interfacing ICs and other combinational logic on the circuit board using VHDL hardware description language.