Aiswaraya Rani K J — Software Engineer
Experienced Hardware Design Engineer with a demonstrated history of working in the Semiconductor industry. Skilled in VHDL, FPGA,RTL Design and Verification. Skills and Languages: Verilog, VHDL, Digital Design, Static Timing Analysis, CDC Tools Handled: Model Sim and QuestaSim, Intel Quartus Prime, Xilinx Vivado, Mentor HDS lint tool,MATLAB AMD Xilinx FPGAs including Versal devices and Intel FPGAs. Protocols handled: Ethernet PTP, PCIe, AXI, SPI, I2C, RMAP etc.. Strong engineering professional with a Bachelor of Technology focused in Electronics and Communications Engineering from College of Engineering ,Kidangoor.
Stackforce AI infers this person is a Semiconductor industry expert specializing in FPGA and RTL design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 11 mos
Skills
- Fpga
- Rtl Design
- Verification
Career Highlights
- Expert in FPGA design and verification.
- Strong background in VHDL and RTL design.
- Proficient in multiple design tools and protocols.
Work Experience
Ericsson
Experienced Engineer - FPGA Design (2 mos)
ProcSys-Processor Systems
Associate Project Lead (RTL Design) (8 mos)
Senior Engineer (RTL Design) (2 yrs 4 mos)
Associate Senior Engineer (RTL Design) (2 yrs 1 mo)
Design Engineer (RTL Design) (2 yrs 4 mos)
Education
Bachelor of Technology at APJ Abdul Kalam Technological University
Higher Secondary CBSE at Jawahar Navodaya Vidyalaya - JNV
