Jan 2025 – Present · 1 yr 4 mos · Hyderabad, Telangana, India · On-site

• SoC Power Optimization | LPM & System Power States | Networking & Hypervisor Awareness | 3nm → 2nm Platforms | Snapdragon® Elite Gen 5
• Engineered SoC‑level low‑power performance optimizations on advanced 3nm architectures, with forward‑looking enablement for 2nm platform bring‑up
• Contributed to power optimization on Snapdragon® Elite Gen 5, achieving ~70% power reduction through deep HW–SW co‑analysis, workload characterization, and system‑level tuning
• Analyzed and validated Low Power Modes (LPMs) across idle, suspend, and runtime scenarios, including clock gating, power‑domain control, and subsystem residency analysis
• Performed kernel‑level debugging and scheduler analysis to identify power inefficiencies related to task placement, wakeups, and latency‑sensitive workloads
• Supported networking and I/O power optimization by analyzing wake‑up sources, interrupt behavior, and traffic‑driven power impact across system power states
• Validated power and performance behavior in hypervisor‑based and multi‑VM environments, including cross‑VM resource sharing and isolation scenarios
• Hands‑on with JTAG and GDB‑based debugging, enabling real‑time validation, boundary‑scan/register monitoring, and root‑cause analysis of silicon‑level power and performance issues
• Conducted log‑driven power profiling and validation using internal tools (Kratos) and platform diagnostics for pre‑silicon and post‑silicon debugging
• Collaborated closely with San Diego teams on power metrics evaluation, remote power profiling, networking/LPM validation, and cross‑platform bring‑up
• Acted as a bridge across silicon, kernel, hypervisor, and system software, driving cohesive power‑performance optimization across the stack